wip

Author: robtaylor

chipflow_lib/platforms/utils.py

@@ -274,7 +274,7 @@ class _BasePackageDef(pydantic.BaseModel, abc.ABC):
     @property
     @abc.abstractmethod
     def pins(self) -> PinSet:
-        "Returns the full set of pins for the package"
+        "Returns the full set of unallocated pins for the package"
         ...
 
     @abc.abstractmethod
@@ -349,9 +349,14 @@ class _BareDiePackageDef(_BasePackageDef):
     height: int
 
     def model_post_init(self, __context):
-        self._ordered_pins = sorted(
-            list(itertools.product((_Side.N, _Side.S), range(self.width))) +
-            list(itertools.product((_Side.W, _Side.E), range(self.height))))
+        pins = (
+            set(itertools.product((_Side.N, _Side.S), range(self.width)))
+            + set(itertools.product((_Side.W, _Side.E), range(self.height)))
+            - set(self.power.values())
+            - set(self.power.clocks.values())
+            - set(self.power.jtag.values())
+        )
+        self._ordered_pins = sorted(pins)
         return super().model_post_init(__context)
 
     @property
@@ -416,11 +421,29 @@ def heartbeat(self) -> Dict[int, Pin]:
         return {0: (_Side.S, 1)}  # South side, pin 1
 
 
-class _PGAPackageDef(_BasePackageDef):
-    """Definiton of a PGA package with `size` pins
-
-    This is package with `size` pins, numbered, with the assumption that adjacent pins
-    are numbered close together.
+class _QuadPackageDef(_BasePackageDef):
+    """Definiton of a package a row of 'width* pins on the top and bottom of the package and 'height' pins
+    on the left and right
+
+    The pins are numbered anti-clockwise from the top left hand pin.
+
+    This includes the following types of package:
+    .. csv-table:
+    :header: "Package", "Description"
+    "BQFP", "bumpered quad flat package"
+    "BQFPH", "bumpered quad flat package with heat spreader"
+    "CQFP", "ceramic quad flat package"
+    "EQFP", "plastic enhanced quad flat package"
+    "FQFP", "fine pitch quad flat package"
+    "LQFP", "low profile quad flat package"
+    "MQFP", "metric quad flat package"
+    "NQFP", "near chip-scale quad flat package."
+    "SQFP", "small quad flat package"
+    "TQFP", "thin quad flat package"
+    "VQFP", "very small quad flat package"
+    "VTQFP", "very thin quad flat package"
+    "TDFN", "thin dual flat no-lead package."
+    "CERQUAD", "low-cost CQFP"
     """
 
     # Used by pydantic to differentate when deserialising
@@ -430,8 +453,13 @@ class _PGAPackageDef(_BasePackageDef):
     height: int
 
     def model_post_init(self, __context):
-        self._ordered_pins = sorted(
-            [str(i) for i in range(1, self.width * 2 + self.height * 2)])
+        pins =(
+            set([str(i) for i in range(1, self.width * 2 + self.height * 2)])
+            - set(self.power.values())
+            - set(self.power.clocks.values())
+            - set(self.power.jtag.values())
+        )
+        self._ordered_pins = sorted(pins)
         return super().model_post_init(__context)
 
 
@@ -517,14 +545,14 @@ def heartbeat(self) -> Dict[int, Pin]:
 
 class Port(pydantic.BaseModel):
     type: str
-    pins: List[str]
+    pins: List[str] | None  # None implies must be allocated at end
     port_name: str
     direction: Optional[str] = None
     options: Optional[dict] = None
 
     @property
     def width(self):
-        return len(self.pins)
+        return len(self.pins) if self.pins else 0
 
 
 class Package(pydantic.BaseModel):
@@ -559,18 +587,13 @@ def add_pad(self, name: str, defn: dict):
                 self.power[name] = Port(type="power", pins=[loc], port_name=name)
             case {"type": "ground", "loc": loc}:
                 self.power[name] = Port(type="ground", pins=[loc], port_name=name)
-            case {"type": "power", "name": name, "voltage": voltage}:
-                # Support for new power pin format
-                # First, get the default pin from the package type
-                power_pin = self.package_type.power[PowerType.POWER]
-                self.power[name] = Port(type="power", pins=[str(power_pin)], options={"voltage": voltage})
-            case {"type": "ground", "name": name}:
-                # Support for new ground pin format
-                ground_pin = self.package_type.power[PowerType.GROUND]
-                self.power[name] = Port(type="ground", pins=[str(ground_pin)])
             case _:
                 pass
 
+    def add_power_domain(self, name: str, defn: dict):
+        self.power[name] = Port(type="power", options=defn)
+        self.power[name] = Port(type="ground", options=defn)
+
     def initialize_from_package_type(self):
         """Initialize standard pins from package type definitions"""
         # Set up clocks

tests/test_config_models.py

@@ -20,12 +20,9 @@ def setUp(self):
                 "top": {},
                 "silicon": {
                     "process": "sky130",
-                    "package": "cf20",
-                    "pads": {
-                        "sys_clk": {"type": "clock", "loc": "114"}
-                    },
+                    "package": "pga144",
                     "power": {
-                        "vdd": {"type": "power", "loc": "1"}
+                        "vdd": {"type": "power"}
                     }
                 }
             }
@@ -35,7 +32,7 @@ def test_config_validation(self):
         """Test that the Config model validates a known-good config."""
         config = Config.model_validate(self.valid_config_dict)
         self.assertEqual(config.chipflow.project_name, "test-chip")
-        self.assertEqual(config.chipflow.silicon.package, "cf20")
+        self.assertEqual(config.chipflow.silicon.package, "pga144")
         self.assertEqual(config.chipflow.silicon.process, Process.SKY130)
 
     def test_pad_config(self):
@@ -66,4 +63,3 @@ def test_nested_structure(self):
         self.assertEqual(len(silicon.power), 1)
         power = silicon.power["vdd"]
         self.assertEqual(power.type, "power")
-        self.assertEqual(power.loc, "1")