Fix some wiring up issues in simulation

Author: robtaylor

chipflow_lib/platforms/sim.py

@@ -81,7 +81,7 @@ def instantiate_ports(self, m: Module):
                 raise ChipFlowError(f"Unable to find clock {name} in pinlock")
 
             port_data = pinlock.package.clocks[name]
-            port = io.SimulationPort(io.Direction.Input, port_data.width, invert=True, name=f"clock-{name}")
+            port = io.SimulationPort(io.Direction.Input, port_data.width, name=f"clock-{name}")
             self._ports[name] = port
 
             if clock == 'default':
@@ -93,7 +93,7 @@ def instantiate_ports(self, m: Module):
 
         for reset, name in self._config["chipflow"]["resets"].items():
             port_data = pinlock.package.resets[name]
-            port = io.SimulationPort(io.Direction.Input, port_data.width, invert=port.invert, name=f"clock-{name}", )
+            port = io.SimulationPort(io.Direction.Input, port_data.width, name=f"reset-{name}", )
             self._ports[name] = port
             rst_buffer = io.Buffer("i", port)
             setattr(m.submodules, reset, rst_buffer)

chipflow_lib/steps/__init__.py

@@ -59,7 +59,8 @@ def _wire_up_ports(m: Module, top, platform):
                 port = platform._ports[port.port_name]
                 if hasattr(wire, 'i'):
                     m.d.comb += wire.i.eq(port.i ^ inv_mask)
-                for d in ['o', 'oe']:
-                    if hasattr(wire, d):
-                        m.d.comb += getattr(port, d).eq(getattr(wire, d) ^ inv_mask)
+                if hasattr(wire, 'o'):
+                        m.d.comb += port.o.eq(wire.o)^ inv_mask
+                if hasattr(wire, 'oe'):
+                        m.d.comb += port.oe.eq(wire.oe)^ inv_mask