Fix up packagepins on top of sim-common

Author: robtaylor

chipflow_lib/platforms/silicon.py

@@ -278,12 +278,14 @@ def instantiate_ports(self, m: Module):
                     self._ports[port.port_name] = SiliconPlatformPort(component, name, port)
 
         for clock in pinlock.port_map.get_clocks():
-            setattr(m.domains, clock.port_name, ClockDomain(name=clock.port_name))
+            domain = name=clock.iomodel['clock_domain_o']
+            setattr(m.domains, domain, ClockDomain(name=domain))
             clk_buffer = io.Buffer("i", self._ports[clock.port_name])
-            setattr(m.submodules, "clk_buffer_" + clock.port_name, clk_buffer)
+            setattr(m.submodules, "clk_buffer_" + domain, clk_buffer)
             m.d.comb += ClockSignal().eq(clk_buffer.i)  #type: ignore[reportAttributeAccessIssue]
 
         for reset in pinlock.port_map.get_resets():
+            domain = name=clock.iomodel['clock_domain_o']
             rst_buffer = io.Buffer("i", self._ports[reset.port_name])
             setattr(m.submodules, reset.port_name, rst_buffer)
             setattr(m.submodules, reset.port_name + "_sync", FFSynchronizer(rst_buffer.i, ResetSignal()))  #type: ignore[reportAttributeAccessIssue]
@@ -326,7 +328,7 @@ def _check_clock_domains(self, fragment, sync_domain=None):
         for clock_domain in fragment.domains.values():
             if clock_domain.name != "sync" or (sync_domain is not None and
                                              clock_domain is not sync_domain):
-                raise ChipFlowError("Only a single clock domain, called 'sync', may be used")
+                raise ChipFlowError(f"Only a single clock domain, called 'sync', may be used: {clock_domain.name}")
             sync_domain = clock_domain
 
         for subfragment, subfragment_name, src_loc in fragment.subfragments:

chipflow_lib/platforms/utils.py

@@ -502,7 +502,7 @@ def get_clocks(self) -> List[Port]:
             for cn, i in c.items():
                 for ni, p in i.items():
                     if p.type == "clock":
-                        ret.append(i)
+                        ret.append(p)
         return ret
 
     def get_resets(self) -> List[Port]:
@@ -511,7 +511,7 @@ def get_resets(self) -> List[Port]:
             for cn, i in c.items():
                 for ni, p in i.items():
                     if p.type == "reset":
-                        ret.append(i)
+                        ret.append(p)
         return ret
 
 
@@ -616,12 +616,12 @@ def _allocate_bringup(self, config: 'Config') -> Component:
         d: Interface = { 'sync-clk': Port(type='clock',
                                           pins=[self.bringup_pins.core_clock],
                                           port_name='sync-clk',
-                                          iomodel=IOModel(width=1, direction=io.Direction.Input)
+                                          iomodel=IOModel(width=1, direction=io.Direction.Input, clock_domain_o="sync")
                                       ),
                           'sync-rst': Port(type='reset',
                                            pins=[self.bringup_pins.core_reset],
                                            port_name='sync-rst',
-                                           iomodel=IOModel(width=1, direction=io.Direction.Input)
+                                           iomodel=IOModel(width=1, direction=io.Direction.Input, clock_domain_o="sync")
                                       )
                        }
         assert config.chipflow.silicon
@@ -630,7 +630,7 @@ def _allocate_bringup(self, config: 'Config') -> Component:
             d['heartbeat'] = Port(type='heartbeat',
                                   pins=[self.bringup_pins.core_heartbeat],
                                   port_name='heartbeat',
-                                  iomodel=IOModel(width=1, direction=io.Direction.Output)
+                                  iomodel=IOModel(width=1, direction=io.Direction.Output, clock_domain_i="sync")
                               )
         #TODO: JTAG
         return {'bringup_pins': d}
@@ -1068,9 +1068,13 @@ def load_pinlock():
     chipflow_root = _ensure_chipflow_root()
     lockfile = pathlib.Path(chipflow_root, 'pins.lock')
     if lockfile.exists():
-        json = lockfile.read_text()
-        return LockFile.model_validate_json(json)
-    raise ChipFlowError("Lockfile pins.lock not found. Run `chipflow pin lock`")
+        try:
+            json = lockfile.read_text()
+            return LockFile.model_validate_json(json)
+        except pydantic.ValidationError:
+            raise ChipFlowError("Lockfile `pins.lock` is misformed. Please remove and rerun chipflow pin lock`")
+
+    raise ChipFlowError("Lockfile `pins.lock` not found. Run `chipflow pin lock`")
 
 
 def top_components(config):
@@ -1084,6 +1088,8 @@ def top_components(config):
             param = name.split('.')[1]
             logger.debug(f"Config {param} = {conf} found for {name}")
             component_configs[param] = conf
+        if name.startswith('_'):
+            raise ChipFlowError(f"Top components cannot start with '_': {name}")
 
     # Second pass: instantiate components
     for name, ref in config.chipflow.top.items():

chipflow_lib/steps/silicon.py

@@ -10,6 +10,7 @@
 import subprocess
 import time
 import urllib3
+from pprint import pformat
 
 import dotenv
 
@@ -44,11 +45,15 @@ def elaborate(self, platform: SiliconPlatform):
 
         top = top_components(self._config)
         logger.debug(f"SiliconTop top = {top}")
+        logger.debug(f"port map ports =\n{pformat(platform.pinlock.port_map.ports)}")
 
         for n, t in top.items():
             setattr(m.submodules, n, t)
 
         for component, iface in platform.pinlock.port_map.ports.items():
+            if component.startswith('_'):
+                logger.debug(f"Ignoring special component {component}")
+                continue
             for iface_name, member, in iface.items():
                 for name, port in member.items():
                     iface = getattr(top[component], iface_name)
@@ -121,14 +126,12 @@ def submit(self, rtlil_path, args):
                 )
         self._chipflow_api_origin = os.environ.get("CHIPFLOW_API_ORIGIN", "https://build.chipflow.org")
 
-        assert self._chipflow_api_key
-        assert self._chipflow_api_origin
 
         with  Halo(text="Submitting...", spinner="dots") as sp:
             fh = None
             submission_name = self.determine_submission_name()
             data = {
-                "projectId": self.config.project_name,
+                "projectId": self.config.chipflow.project_name,
                 "name": submission_name,
             }
 
@@ -178,6 +181,8 @@ def network_err(e):
 
             build_submit_url = f"{self._chipflow_api_origin}/build/submit"
 
+            assert self._chipflow_api_key
+            assert self._chipflow_api_origin
             try:
                 resp = requests.post(
                     build_submit_url,