Make wiring up ports common code and fix invert case

Author: robtaylor

chipflow_lib/pin_lock.py

@@ -62,6 +62,9 @@ def allocate_pins(name: str, member: Dict[str, Any], pins: List[str], port_name:
                          'type': 'io',
                          'port_name': port_name,
                          'options': options}
+        if 'invert' in sig and sig['invert']:
+            pin_map[name]['invert'] = sig['invert']
+
         logger.debug(f"added '{name}':{pin_map[name]} to pin_map")
         return pin_map, pins[width:]
     elif member['type'] == 'interface':

chipflow_lib/platforms/silicon.py

@@ -292,7 +292,7 @@ def instantiate_ports(self, m: Module):
             setattr(m.submodules, reset, rst_buffer)
             setattr(m.submodules, reset + "_sync", FFSynchronizer(rst_buffer.i, ResetSignal()))
 
-        self.pinlock = pinlock
+        self._pinlock = pinlock
 
     def request(self, name=None, **kwargs):
         if "$" in name:

chipflow_lib/platforms/sim.py

@@ -73,7 +73,8 @@ def instantiate_ports(self, m: Module):
         for component, iface in pinlock.port_map.items():
             for k, v in iface.items():
                 for name, port in v.items():
-                    self._ports[port.port_name] = io.SimulationPort(port.direction, port.width, invert=port.invert, name=f"{component}-{name}")
+                   invert = port.invert if port.invert else False
+                   self._ports[port.port_name] = io.SimulationPort(port.direction, port.width, invert=invert, name=f"{component}-{name}")
 
         for clock, name in self._config["chipflow"]["clocks"].items():
             if name not in pinlock.package.clocks:

chipflow_lib/platforms/utils.py

@@ -376,7 +376,7 @@ class Port(pydantic.BaseModel):
     pins: List[str]
     port_name: str
     direction: Optional[str] = None
-    invert: Union[bool, Iterable[bool]] = False
+    invert: Optional[Iterable[bool]] = None
     options: Optional[dict] = None
 
     @property

chipflow_lib/steps/__init__.py

@@ -5,6 +5,10 @@
 import os
 from abc import ABC
 
+from amaranth import Module
+
+from ..platforms.utils import IOSignature
+
 def setup_amaranth_tools():
     _amaranth_settings = {
         "AMARANTH_USE_YOSYS": "system",
@@ -36,3 +40,26 @@ def build_cli_parser(self, parser):
     def run_cli(self, args):
         "Called when this step's is used from `chipflow` command"
         self.build()
+
+
+def _wire_up_ports(m: Module, top, platform):
+    for n, t in top.items():
+        setattr(m.submodules, n, t)
+
+    for component, iface in platform._pinlock.port_map.items():
+        for iface_name, member, in iface.items():
+            for name, port in member.items():
+                iface = getattr(top[component], iface_name)
+                wire = (iface if isinstance(iface.signature, IOSignature)
+                        else getattr(iface, name))
+                if port.invert:
+                    inv_mask = sum(inv << bit for bit, inv in enumerate(port.invert))
+                else:
+                    inv_mask = 0
+                port = platform._ports[port.port_name]
+                if hasattr(wire, 'i'):
+                    m.d.comb += wire.i.eq(port.i ^ inv_mask)
+                for d in ['o', 'oe']:
+                    if hasattr(wire, d):
+                        m.d.comb += getattr(port, d).eq(getattr(wire, d) ^ inv_mask)
+

chipflow_lib/steps/silicon.py

@@ -16,7 +16,7 @@
 from amaranth import *
 from halo import Halo
 
-from . import StepBase
+from . import StepBase, _wire_up_ports
 from .. import ChipFlowError
 from ..cli import log_level
 from ..platforms import SiliconPlatform, top_interfaces, load_pinlock
@@ -44,16 +44,7 @@ def elaborate(self, platform: SiliconPlatform):
         top, interfaces = top_interfaces(self._config)
         logger.debug(f"SiliconTop top = {top}, interfaces={interfaces}")
 
-        for n, t in top.items():
-            setattr(m.submodules, n, t)
-
-        for component, iface in platform.pinlock.port_map.items():
-            for iface_name, member, in iface.items():
-                for name, port in member.items():
-                    iface = getattr(top[component], iface_name)
-                    wire = (iface if isinstance(iface.signature, IOSignature)
-                            else getattr(iface, name))
-                    platform.ports[port.port_name].wire(m, wire)
+        _wire_up_ports(m, top, platform)
         return m
 
 

chipflow_lib/steps/sim.py

@@ -12,8 +12,8 @@
 
 from amaranth import *
 
+from . import StepBase, _wire_up_ports
 from .. import ChipFlowError, _ensure_chipflow_root
-from . import StepBase
 from ..platforms import SimPlatform, top_interfaces
 from ..platforms.sim import VARIABLES, TASKS, DOIT_CONFIG
 
@@ -92,22 +92,7 @@ def build(self):
         top, interfaces = top_interfaces(self._config)
         logger.debug(f"SiliconTop top = {top}, interfaces={interfaces}")
 
-        for n, t in top.items():
-            setattr(m.submodules, n, t)
-
-        for component, iface in self._platform._pinlock.port_map.items():
-            for iface_name, member, in iface.items():
-                for name, port in member.items():
-                    iface = getattr(top[component], iface_name)
-                    wire = (iface if isinstance(iface.signature, IOSignature)
-                            else getattr(iface, name))
-                    port = self._platform._ports[port.port_name]
-                    if hasattr(wire, 'i'):
-                        m.d.comb += wire.i.eq(port.i)
-                    for d in ['o', 'oe']:
-                        if hasattr(wire, d):
-                            m.d.comb += getattr(port, d).eq(getattr(wire, d))
-
+        _wire_up_ports(m, top, self._platform)
 
         #FIXME: common source for build dir
         self._platform.build(m)