Rename PinSignature to IOSignature

Avoids clash with amaranth-soc entity of same name

Author: robtaylor

chipflow_lib/pin_lock.py

@@ -53,7 +53,7 @@ def allocate_pins(name: str, member: Dict[str, Any], pins: List[str], port_name:
 
     if member['type'] == 'interface' and 'annotations' in member \
        and PIN_ANNOTATION_SCHEMA in member['annotations']:
-        logger.debug("matched PinSignature {sig}")
+        logger.debug("matched IOSignature {sig}")
         sig = member['annotations'][PIN_ANNOTATION_SCHEMA]
         width = sig['width']
         options = sig['options']
@@ -72,7 +72,7 @@ def allocate_pins(name: str, member: Dict[str, Any], pins: List[str], port_name:
             logger.debug(f"{pin_map},{_map}")
         return pin_map, pins
     elif member['type'] == 'port':
-        logger.warning(f"Port '{name}' has no PinSignature, pin allocation likely to be wrong")
+        logger.warning(f"Port '{name}' has no IOSignature, pin allocation likely to be wrong")
         width = member['width']
         pin_map[name] = {'pins': pins[0:width],
                               'direction': member['dir'],

chipflow_lib/platforms/__init__.py

@@ -10,6 +10,6 @@
 from .sim import *
 from .utils import *
 
-__all__ = ['PIN_ANNOTATION_SCHEMA', 'PinSignature',
-           'OutputPinSignature', 'InputPinSignature', 'BidirPinSignature',
+__all__ = ['PIN_ANNOTATION_SCHEMA', 'IOSignature',
+           'OutputIOSignature', 'InputIOSignature', 'BidirIOSignature',
            'load_pinlock', "PACKAGE_DEFINITIONS", 'top_interfaces']

chipflow_lib/platforms/utils.py

@@ -17,8 +17,8 @@
 from .. import ChipFlowError, _ensure_chipflow_root, _get_cls_by_reference
 
 
-__all__ = ['PIN_ANNOTATION_SCHEMA', 'PinSignature',
-           'OutputPinSignature', 'InputPinSignature', 'BidirPinSignature',
+__all__ = ['PIN_ANNOTATION_SCHEMA', 'IOSignature',
+           'OutputIOSignature', 'InputIOSignature', 'BidirIOSignature',
            'load_pinlock', "PACKAGE_DEFINITIONS", 'top_interfaces', 'LockFile',
            'Package', 'PortMap', 'Port']
 
@@ -65,11 +65,11 @@ def as_json(self):  # type: ignore
 PIN_ANNOTATION_SCHEMA = str(_chipflow_schema_uri("pin-annotation", 0))
 
 
-class PinSignature(wiring.Signature):
+class IOSignature(wiring.Signature):
     """An :py:obj:`Amaranth Signature <amaranth.lib.wiring.Signature>` used to decorate wires that would usually be brought out onto a port on the package.
     This class is generally not directly used.
     Instead, you would typically utilize the more specific
-    :py:obj:`InputPinSignature`, :py:obj:`OutputPinSignature`, or :py:obj:`BidirPinSignature` for defining pin interfaces.
+    :py:obj:`InputIOSignature`, :py:obj:`OutputIOSignature`, or :py:obj:`BidirIOSignature` for defining pin interfaces.
 
     :param direction: Input, Output or Bidir
     :param width: width of port, default is 1
@@ -129,32 +129,32 @@ def annotations(self, *args):
 
     def __repr__(self):
         opts = ', '.join(f"{k}={v}" for k, v in self._options.items())
-        return f"PinSignature({self._direction}, {self._width}, {opts})"
+        return f"IOSignature({self._direction}, {self._width}, {opts})"
 
 
-def OutputPinSignature(width, **kwargs):
+def OutputIOSignature(width, **kwargs):
     """This creates an :py:obj:`Amaranth Signature <amaranth.lib.wiring.Signature>` which is then used to decorate package output signals
     intended for connection to the physical pads of the integrated circuit package.
 
     :param width: specifies the number of individual output wires within this port, each of which will correspond to a separate physical pad on the integrated circuit package.
     :type width: int
     :param init: a  :ref:`const-castable object <lang-constcasting>` for the initial values of the port
     """
-    return PinSignature(io.Direction.Output, width=width, **kwargs)
+    return IOSignature(io.Direction.Output, width=width, **kwargs)
 
 
-def InputPinSignature(width, **kwargs):
+def InputIOSignature(width, **kwargs):
     """This creates an :py:obj:`Amaranth Signature <amaranth.lib.wiring.Signature>` which is then used to decorate package input signals
     intended for connection to the physical pads of the integrated circuit package.
 
     :param width: specifies the number of individual input wires within this port, each of which will correspond to a separate physical pad on the integrated circuit package.
     :type width: int
     :param init: a  :ref:`const-castable object <lang-constcasting>` for the initial values of the port
     """
-    return PinSignature(io.Direction.Input, width=width, **kwargs)
+    return IOSignature(io.Direction.Input, width=width, **kwargs)
 
 
-def BidirPinSignature(width, **kwargs):
+def BidirIOSignature(width, **kwargs):
     """This creates an :py:obj:`Amaranth Signature <amaranth.lib.wiring.Signature>` which is then used to decorate package bi-directional signals
     intended for connection to the physical pads of the integrated circuit package.
 
@@ -164,7 +164,7 @@ def BidirPinSignature(width, **kwargs):
     :type all_have_oe: bool, optional
     :param init: a  :ref:`const-castable object <lang-constcasting>` for the initial values of the port
     """
-    return PinSignature(io.Direction.Bidir, width=width, **kwargs)
+    return IOSignature(io.Direction.Bidir, width=width, **kwargs)
 
 
 Pin = Union[tuple, str]

chipflow_lib/steps/silicon.py

@@ -20,7 +20,7 @@
 from .. import ChipFlowError
 from ..cli import log_level
 from ..platforms import SiliconPlatform, top_interfaces, load_pinlock
-from ..platforms.utils import PinSignature
+from ..platforms.utils import IOSignature
 
 
 logger = logging.getLogger(__name__)
@@ -52,7 +52,7 @@ def elaborate(self, platform: SiliconPlatform):
             for iface_name, member, in iface.items():
                 for name, port in member.items():
                     iface = getattr(top[component], iface_name)
-                    wire = (iface if isinstance(iface.signature, PinSignature)
+                    wire = (iface if isinstance(iface.signature, IOSignature)
                             else getattr(iface, name))
                     platform.ports[port.port_name].wire(m, wire)
         return m

docs/chipflow-commands.rst

@@ -10,7 +10,7 @@ It implements several subcommands, which can be customised or added to in the ``
 ---------------------
 
 The ``chipflow pin lock`` command performs pin locking for the current design.
-For every new top level interface with containing external pins with a ``PinSignature`` that is discovered, the necessary number of package pins is allocated and the mapping saved in the ``pins.lock`` file.
+For every new top level interface with containing external pins with a ``IOSignature`` that is discovered, the necessary number of package pins is allocated and the mapping saved in the ``pins.lock`` file.
 This means that, unless the ``pins.lock`` file is deleted or manually modified, the pin assignments of all existing pins will always remain the same.
 
 ``chipflow silicon``

tests/fixtures/mock_top.py

@@ -3,26 +3,26 @@
 from amaranth.lib import wiring
 from amaranth.lib.wiring import In, Out
 
-from chipflow_lib.platforms import InputPinSignature, OutputPinSignature, BidirPinSignature
+from chipflow_lib.platforms import InputIOSignature, OutputIOSignature, BidirIOSignature
 
 __all__ = ["MockTop"]
 
 TestSignature1 = wiring.Signature({
-    "a": In(InputPinSignature(1)),
-    "b": In(InputPinSignature(5)),
-    "c": Out(OutputPinSignature(1)),
-    "d": Out(OutputPinSignature(10)),
-    "e": In(BidirPinSignature(1)),
-    "f": In(BidirPinSignature(7)),
+    "a": In(InputIOSignature(1)),
+    "b": In(InputIOSignature(5)),
+    "c": Out(OutputIOSignature(1)),
+    "d": Out(OutputIOSignature(10)),
+    "e": In(BidirIOSignature(1)),
+    "f": In(BidirIOSignature(7)),
 })
 
 TestSignature2 = wiring.Signature({
-    "a": Out(OutputPinSignature(1)),
-    "b": Out(OutputPinSignature(5)),
-    "c": In(InputPinSignature(1)),
-    "d": In(InputPinSignature(10)),
-    "e": Out(BidirPinSignature(1)),
-    "f": Out(BidirPinSignature(7)),
+    "a": Out(OutputIOSignature(1)),
+    "b": Out(OutputIOSignature(5)),
+    "c": In(InputIOSignature(1)),
+    "d": In(InputIOSignature(10)),
+    "e": Out(BidirIOSignature(1)),
+    "f": Out(BidirIOSignature(7)),
 })
 
 

tests/test_utils.py

@@ -7,7 +7,7 @@
 
 from amaranth.lib import io
 
-from chipflow_lib.platforms.utils import PinSignature, OutputPinSignature, InputPinSignature, BidirPinSignature, _PinAnnotation, _PinAnnotationModel
+from chipflow_lib.platforms.utils import IOSignature, OutputIOSignature, InputIOSignature, BidirIOSignature, _PinAnnotation, _PinAnnotationModel
 from chipflow_lib.platforms.utils import PinList, _group_consecutive_items,_find_contiguous_sequence, _Side
 
 
@@ -53,32 +53,32 @@ def test_find_contiguous_sequence():
 
 
 def test_pin_signature():
-    sig_bidir = PinSignature(io.Direction.Bidir, width=8)
-    assert isinstance(sig_bidir, PinSignature)
+    sig_bidir = IOSignature(io.Direction.Bidir, width=8)
+    assert isinstance(sig_bidir, IOSignature)
     assert sig_bidir._direction == io.Direction.Bidir
     assert sig_bidir._width == 8
     assert "o" in sig_bidir.members
     assert "oe" in sig_bidir.members
     assert "i" in sig_bidir.members
 
-    sig_output = OutputPinSignature(width=4)
-    assert isinstance(sig_output, PinSignature)
+    sig_output = OutputIOSignature(width=4)
+    assert isinstance(sig_output, IOSignature)
     assert sig_output._direction == io.Direction.Output
     assert sig_output._width == 4
     assert "o" in sig_output.members
     assert "oe" not in sig_output.members
     assert "i" not in sig_output.members
 
-    sig_input = InputPinSignature(width=2)
-    assert isinstance(sig_input, PinSignature)
+    sig_input = InputIOSignature(width=2)
+    assert isinstance(sig_input, IOSignature)
     assert sig_input._direction == io.Direction.Input
     assert sig_input._width == 2
     assert "o" not in sig_input.members
     assert "oe" not in sig_output.members
     assert "i" in sig_input.members
 
-    sig_bidir_fn = BidirPinSignature(width=1)
-    assert isinstance(sig_bidir_fn, PinSignature)
+    sig_bidir_fn = BidirIOSignature(width=1)
+    assert isinstance(sig_bidir_fn, IOSignature)
     assert sig_bidir_fn._direction == io.Direction.Bidir
     assert sig_bidir_fn._width == 1
     assert "o" in sig_bidir_fn.members

tests/test_utils_additional.py

@@ -12,7 +12,7 @@
     _PinAnnotationModel,
     _PinAnnotation,
     PIN_ANNOTATION_SCHEMA,
-    PinSignature,
+    IOSignature,
     _Side,
     _BasePackageDef,
     _BareDiePackageDef,
@@ -69,12 +69,12 @@ def test_pin_annotation(self):
         self.assertEqual(json_data["options"], {})
 
 
-class TestPinSignature(unittest.TestCase):
+class TestIOSignature(unittest.TestCase):
     def test_pin_signature_properties(self):
-        """Test PinSignature properties"""
+        """Test IOSignature properties"""
         # Create signature with options
         options = {"all_have_oe": True, "init": 0}
-        sig = PinSignature(io.Direction.Bidir, width=4, all_have_oe=True, init=0)
+        sig = IOSignature(io.Direction.Bidir, width=4, all_have_oe=True, init=0)
 
         # Test properties
         self.assertEqual(sig.direction, io.Direction.Bidir)
@@ -83,15 +83,15 @@ def test_pin_signature_properties(self):
 
         # Test __repr__ - actual representation depends on Direction enum's representation
         repr_string = repr(sig)
-        self.assertIn("PinSignature", repr_string)
+        self.assertIn("IOSignature", repr_string)
         self.assertIn("4", repr_string)
         self.assertIn("all_have_oe=True", repr_string)
         self.assertIn("init=0", repr_string)
 
     def test_pin_signature_annotations(self):
-        """Test PinSignature annotations method"""
+        """Test IOSignature annotations method"""
         # Create signature
-        sig = PinSignature(io.Direction.Output, width=8, init=42)
+        sig = IOSignature(io.Direction.Output, width=8, init=42)
 
         # Create a mock object to pass to annotations
         mock_obj = object()