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1 parent 10c3f51 commit 6fdb370Copy full SHA for 6fdb370
chipflow_lib/steps/silicon.py
@@ -12,6 +12,7 @@
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import dotenv
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from amaranth import *
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+from amaranth.lib.wiring import PureInterface
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from . import StepBase
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from .. import ChipFlowError
@@ -46,10 +47,10 @@ def elaborate(self, platform: SiliconPlatform):
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for component, iface in platform.pinlock.port_map.items():
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for iface_name, member, in iface.items():
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for name, port in member.items():
- platform.ports[port.port_name].wire(
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- m,
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- getattr(getattr(top[component], iface_name), name)
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- )
+ iface = getattr(top[component], iface_name)
+ wire = (iface if isinstance(iface, PureInterface)
+ else getattr(iface, name))
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+ platform.ports[port.port_name].wire(m, wire)
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return m
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