Update sim infrastructure so it all lives in chipflow-lib

Author: robtaylor

chipflow_lib/__init__.py

@@ -44,7 +44,7 @@ def _ensure_chipflow_root():
 
     if os.environ["CHIPFLOW_ROOT"] not in sys.path:
         sys.path.append(os.environ["CHIPFLOW_ROOT"])
-    _ensure_chipflow_root.root = os.environ["CHIPFLOW_ROOT"]
+    _ensure_chipflow_root.root = Path(os.environ["CHIPFLOW_ROOT"]).absolute()
     return _ensure_chipflow_root.root
 
 

chipflow_lib/platforms/silicon.py

@@ -139,6 +139,7 @@ def pins(self):
     def invert(self):
         return self._invert
 
+
     def __len__(self):
         if self._direction is io.Direction.Input:
             return len(self._i)

chipflow_lib/platforms/sim.py

@@ -1,96 +1,144 @@
 # SPDX-License-Identifier: BSD-2-Clause
 
 import os
+import sys
 from pathlib import Path
 
 from amaranth import *
+from amaranth.lib import io
 from amaranth.back import rtlil
+from amaranth.hdl._ir import PortDirection
+from amaranth.lib.cdc import FFSynchronizer
 
+from .. import ChipFlowError
+from .utils import load_pinlock
 
 __all__ = ["SimPlatform"]
 
 
 class SimPlatform:
-    def __init__(self):
+
+    def __init__(self, config):
         self.build_dir = os.path.join(os.environ['CHIPFLOW_ROOT'], 'build', 'sim')
         self.extra_files = dict()
-        self.clk = Signal()
-        self.rst = Signal()
-        self.buttons = Signal(2)
         self.sim_boxes = dict()
+        self._ports = {}
+        self._config = config
 
     def add_file(self, filename, content):
         if not isinstance(content, (str, bytes)):
             content = content.read()
         self.extra_files[filename] = content
 
-    def add_model(self, inst_type, iface, edge_det=[]):
-        conns = dict(i_clk=ClockSignal(), a_keep=True)
-
-        def is_model_out(field_name):
-            assert field_name.endswith("_o") or field_name.endswith("_oe") or field_name.endswith("_i"), field_name
-            return field_name.endswith("_i")
-        for field_name in iface.signature.members:
-            if is_model_out(field_name):
-                conns[f"o_{field_name}"] = getattr(iface, field_name)
-            else:
-                conns[f"i_{field_name}"] = getattr(iface, field_name)
-        if inst_type not in self.sim_boxes:
-            box = 'attribute \\blackbox 1\n'
-            box += 'attribute \\cxxrtl_blackbox 1\n'
-            box += 'attribute \\keep 1\n'
-            box += f'module \\{inst_type}\n'
-            box += '  attribute \\cxxrtl_edge "a"\n'
-            box += '  wire width 1 input 0 \\clk\n'
-            for i, ((field_name,), _, field) in enumerate(iface.signature.flatten(iface)):
-                field_width = Shape.cast(field.shape()).width
-                if field_name in edge_det:
-                    box += '  attribute \\cxxrtl_edge "a"\n'
-                box += f'  wire width {field_width} {"output" if is_model_out(field_name) else "input"} {i} \\{field_name}\n' # noqa: E501
-            box += 'end\n\n'
-            self.sim_boxes[inst_type] = box
-        return Instance(inst_type, **conns)
-
-    def add_monitor(self, inst_type, iface):
-        conns = dict(i_clk=ClockSignal(), a_keep=True)
-        for field_name in iface.signature.members:
-            conns[f'i_{field_name}'] = getattr(iface, field_name)
-        if inst_type not in self.sim_boxes:
-            box = 'attribute \\blackbox 1\n'
-            box += 'attribute \\cxxrtl_blackbox 1\n'
-            box += 'attribute \\keep 1\n'
-            box += f'module \\{inst_type}\n'
-            box += '  attribute \\cxxrtl_edge "a"\n'
-            box += '  wire width 1 input 0 \\clk\n'
-            for i, ((field_name,), _, field) in enumerate(iface.signature.flatten(iface)):
-                field_width = Shape.cast(field.shape()).width
-                box += f'  wire width {field_width} input {i + 1} \\{field_name}\n'
-            box += 'end\n\n'
-            self.sim_boxes[inst_type] = box
-        return Instance(inst_type, **conns)
-
     def build(self, e):
         Path(self.build_dir).mkdir(parents=True, exist_ok=True)
 
-        output = rtlil.convert(e, name="sim_top", ports=[self.clk, self.rst, self.buttons], platform=self)
+        ports = []
+        for port_name, port in self._ports.items():
+            if port.direction in (io.Direction.Input, io.Direction.Bidir):
+                ports.append((f"io${port_name}$i", port.i, PortDirection.Input))
+            if port.direction in (io.Direction.Output, io.Direction.Bidir):
+                ports.append((f"io${port_name}$o", port.o, PortDirection.Output))
+            if port.direction is io.Direction.Bidir:
+                ports.append((f"io${port_name}$oe", port.oe, PortDirection.Output))
+
+        output = rtlil.convert(e, name="sim_top", ports=ports, platform=self)
 
         top_rtlil = Path(self.build_dir) / "sim_soc.il"
         with open(top_rtlil, "w") as rtlil_file:
             for box_content in self.sim_boxes.values():
                 rtlil_file.write(box_content)
             rtlil_file.write(output)
+
         top_ys = Path(self.build_dir) / "sim_soc.ys"
         with open(top_ys, "w") as yosys_file:
             for extra_filename, extra_content in self.extra_files.items():
                 extra_path = Path(self.build_dir) / extra_filename
                 with open(extra_path, "w") as extra_file:
                     extra_file.write(extra_content)
                 if extra_filename.endswith(".il"):
-                    print(f"read_rtlil {extra_filename}", file=yosys_file)
+                    print(f"read_rtlil {extra_path}", file=yosys_file)
                 else:
                     # FIXME: use -defer (workaround for YosysHQ/yosys#4059)
-                    print(f"read_verilog {extra_filename}", file=yosys_file)
+                    print(f"read_verilog {extra_path}", file=yosys_file)
             print("read_rtlil sim_soc.il", file=yosys_file)
             print("hierarchy -top sim_top", file=yosys_file)
-            # FIXME: use the default -O6 (workaround for YosysHQ/yosys#4227)
-            print("write_cxxrtl -O4 -header sim_soc.cc", file=yosys_file)
+            print("write_cxxrtl -header sim_soc.cc", file=yosys_file)
+
+    def instantiate_ports(self, m: Module):
+        if hasattr(self, "_pinlock"):
+            return
+
+        pinlock = load_pinlock()
+        for component, iface in pinlock.port_map.items():
+            for k, v in iface.items():
+                for name, port in v.items():
+                    self._ports[port.port_name] = io.SimulationPort(port.direction, port.width, invert=port.invert, name=f"{component}-{name}")
+
+        for clock, name in self._config["chipflow"]["clocks"].items():
+            if name not in pinlock.package.clocks:
+                raise ChipFlowError("Unable to find clock {name} in pinlock")
+
+            port_data = pinlock.package.clocks[name]
+            port = io.SimulationPort(io.Direction.Input, port_data.width, invert=True, name=f"clock-{name}")
+            self._ports[name] = port
+
+            if clock == 'default':
+                clock = 'sync'
+            setattr(m.domains, clock, ClockDomain(name=clock))
+            clk_buffer = io.Buffer("i", port)
+            setattr(m.submodules, "clk_buffer_" + clock, clk_buffer)
+            m.d.comb += ClockSignal().eq(clk_buffer.i)
+
+        for reset, name in self._config["chipflow"]["resets"].items():
+            port_data = pinlock.package.resets[name]
+            port = io.SimulationPort(io.Direction.Input, port_data.width, invert=port.invert, name=f"clock-{name}", )
+            self._ports[name] = port
+            rst_buffer = io.Buffer("i", port)
+            setattr(m.submodules, reset, rst_buffer)
+            setattr(m.submodules, reset + "_sync", FFSynchronizer(rst_buffer.i, ResetSignal()))
+
+        self._pinlock = pinlock
+
+
+
+
+VARIABLES = {
+    "OUTPUT_DIR": "./build/sim",
+    "ZIG_CXX": f"{sys.executable} -m ziglang c++",
+    "CXXFLAGS": "-O3 -g -std=c++17 -Wno-array-bounds -Wno-shift-count-overflow -fbracket-depth=1024",
+    "DEFINES": "-DPROJECT_ROOT=\\\"{PROJECT_ROOT}\\\" -DBUILD_DIR=\\\"{BUILD_DIR}\\\"",
+    "INCLUDES": "-I {OUTPUT_DIR} -I {COMMON_DIR} -I {COMMON_DIR}/vendor -I {RUNTIME_DIR}",
+}
+DOIT_CONFIG = {'action_string_formatting': 'both'}
+
+BUILD_SIM = {
+        "name": "build_sim",
+        "actions": [
+            "{ZIG_CXX} {CXXFLAGS} {INCLUDES} {DEFINES} -o {OUTPUT_DIR}/sim_soc{EXE} "
+            "{OUTPUT_DIR}/sim_soc.cc {SOURCE_DIR}/main.cc {COMMON_DIR}/models.cc"
+            ],
+        "targets": [
+            "{OUTPUT_DIR}/sim_soc{EXE}"
+        ],
+        "file_dep": [
+            "{OUTPUT_DIR}/sim_soc.cc",
+            "{OUTPUT_DIR}/sim_soc.h",
+            "{SOURCE_DIR}/main.cc",
+            "{COMMON_DIR}/models.cc",
+            "{COMMON_DIR}/models.h",
+            "{COMMON_DIR}/vendor/nlohmann/json.hpp",
+            "{COMMON_DIR}/vendor/cxxrtl/cxxrtl_server.h",
+        ],
+    }
+
+SIM_CXXRTL = {
+        "name": "sim_cxxrtl",
+        "actions": ["cd {OUTPUT_DIR} && pdm run yowasp-yosys sim_soc.ys"],
+        "targets": ["{OUTPUT_DIR}/sim_soc.cc", "{OUTPUT_DIR}/sim_soc.h"],
+        "file_dep": ["{OUTPUT_DIR}/sim_soc.ys", "{OUTPUT_DIR}/sim_soc.il"],
+    }
+
+TASKS = [BUILD_SIM, SIM_CXXRTL]
+
+

chipflow_lib/platforms/utils.py

@@ -6,7 +6,7 @@
 import pydantic
 
 from collections import OrderedDict, deque
-from collections.abc import MutableMapping
+from collections.abc import MutableMapping, Iterable
 from pprint import pformat
 from typing import Set, List, Dict, Optional, Union, Literal
 
@@ -73,11 +73,16 @@ class IOSignature(wiring.Signature):
 
     :param direction: Input, Output or Bidir
     :param width: width of port, default is 1
-    :param all_have_oe: controls whether each output wire is associated with an individual Output Enable bit or a single OE bit will be used for entire port, the default value is False, indicating that a single OE bit controls the entire port.
+    :param invert: Polarity inversion. If the value is a simple :class:`bool`, it specifies inversion for
+         the entire port. If the value is an iterable of :class:`bool`, the iterable must have the
+         same length as the width of :py:`io`, and the inversion is specified for individual wires.
+    :param all_have_oe: controls whether each output wire is associated with an individual Output Enable bit
+         or a single OE bit will be used for entire port, the default value is False, indicating that a
+         single OE bit controls the entire port.
     :param init: a  :ref:`const-castable object <lang-constcasting>` for the initial values of the port
     """
 
-    def __init__(self, direction: io.Direction, width: int = 1, all_have_oe: bool = False, init = None):
+    def __init__(self, direction: io.Direction, width: int = 1, invert: Union[bool,Iterable[bool]] = False, all_have_oe: bool = False, init = None):
         self._direction = direction
         self._width = width
         self._init = init
@@ -98,6 +103,17 @@ def __init__(self, direction: io.Direction, width: int = 1, all_have_oe: bool =
                 "all_have_oe": all_have_oe,
                 "init": init,
                 }
+        match invert:
+            case bool():
+                self._invert = (invert,) * self._width
+            case Iterable():
+              self._invert = tuple(invert)
+              if len(self._invert) != self._width:
+                  raise ValueError(f"Length of 'invert' ({len(self._invert)}) doesn't match "
+                                   f"length of 'io' ({len(self._io)})")
+            case _:
+                raise TypeError(f"'invert' must be a bool or iterable of bool, not {invert!r}")
+
 
         super().__init__(sig)
 
@@ -110,6 +126,10 @@ def width(self) -> int:
         "The width of the IO port, in wires"
         return self._width
 
+    def invert(self) -> int:
+        "A tuple as wide as the IO port, with a bool for the polarity inversion for each wire"
+        return self._invert
+
     def options(self) -> dict:
         """
         Options set on the io port at construction
@@ -356,6 +376,7 @@ class Port(pydantic.BaseModel):
     pins: List[str]
     port_name: str
     direction: Optional[str] = None
+    invert: Union[bool, Iterable[bool]] = False
     options: Optional[dict] = None
 
     @property

chipflow_lib/steps/silicon.py

@@ -20,7 +20,6 @@
 from .. import ChipFlowError
 from ..cli import log_level
 from ..platforms import SiliconPlatform, top_interfaces, load_pinlock
-from ..platforms.utils import IOSignature
 
 
 logger = logging.getLogger(__name__)