Changes to support picosoc with custom Verilog

Signed-off-by: gatecat <gatecat@ds0.me>

Author: gatecat

chipflow_lib/platforms/__init__.py

@@ -17,10 +17,10 @@
 from ._sky130 import Sky130DriveMode
 from ._signatures import (
         JTAGSignature, SPISignature, I2CSignature, UARTSignature, GPIOSignature, QSPIFlashSignature,
-        attach_data, SoftwareDriverSignature, SoftwareBuild
+        attach_data, SoftwareDriverSignature, SoftwareBuild, BinaryData
         )
 
-__all__ = ['IO_ANNOTATION_SCHEMA', 'IOSignature',
+__all__ = ['BinaryData', 'IO_ANNOTATION_SCHEMA', 'IOSignature',
            'IOModel', 'IOModelOptions', 'IOTripPoint',
            'OutputIOSignature', 'InputIOSignature', 'BidirIOSignature',
            'SiliconPlatformPort', 'SiliconPlatform',

chipflow_lib/platforms/_signatures.py

@@ -56,6 +56,23 @@ def __init__(self, *, sources: list[Path], includes: list[Path] = [], include_di
         self.include_dirs = list(include_dirs)
         self.offset = offset
 
+@dataclass
+class BinaryData:
+    """
+    This holds the information needed for building software and providing the built outcome
+    """
+    offset: int
+    filename: Path
+    build_dir: Path
+    type: Literal["BinaryData"] = "BinaryData"
+
+    def __init__(self, *, filename: Path, offset=0):
+        self.build_dir = _ensure_chipflow_root() / 'build' / 'software'
+        if Path(filename).is_absolute():
+            self.filename = filename
+        else:
+            self.filename = self.build_dir / filename
+        self.offset = offset
 
 _T_DataClass = TypeVar('_T_DataClass', bound=DataclassProtocol)
 class Data(TypedDict, Generic[_T_DataClass]):
@@ -204,8 +221,9 @@ def __chipflow_parameters__(self):
 
 def attach_data(external_interface: wiring.PureInterface, component: wiring.Component, data: DataclassProtocol):
     data_dict: Data = {'data':data}
-    setattr(component.signature, '__chipflow_data__', data_dict)
-    amaranth_annotate(Data, DATA_SCHEMA, '__chipflow_data__', decorate_object=True)(component.signature)
+    if component is not None:
+        setattr(component.signature, '__chipflow_data__', data_dict)
+        amaranth_annotate(Data, DATA_SCHEMA, '__chipflow_data__', decorate_object=True)(component.signature)
     setattr(external_interface.signature, '__chipflow_data__', data_dict)
     amaranth_annotate(Data, DATA_SCHEMA, '__chipflow_data__', decorate_object=True)(external_interface.signature)
 

chipflow_lib/platforms/sim.py

@@ -21,7 +21,7 @@
 from .. import ChipFlowError, _ensure_chipflow_root
 from ._signatures import (
         I2CSignature, GPIOSignature, UARTSignature, SPISignature, QSPIFlashSignature,
-        SIM_ANNOTATION_SCHEMA, DATA_SCHEMA, SimInterface, SoftwareBuild
+        SIM_ANNOTATION_SCHEMA, DATA_SCHEMA, SimInterface, SoftwareBuild, BinaryData
         )
 from ._utils import load_pinlock, Interface
 
@@ -220,6 +220,10 @@ def build(self, e, top):
                 and annotations[DATA_SCHEMA]['data']['type'] == "SoftwareBuild":
                     sim_data[interface] = TypeAdapter(SoftwareBuild).validate_python(annotations[DATA_SCHEMA]['data'])
 
+                if DATA_SCHEMA in annotations \
+                and annotations[DATA_SCHEMA]['data']['type'] == "BinaryData":
+                    sim_data[interface] = TypeAdapter(BinaryData).validate_python(annotations[DATA_SCHEMA]['data'])
+
         data_load = []
         for i,d in sim_data.items():
             args = [f"0x{d.offset:X}U"]