Convert strategic examples to testable doctests

Phase 3 of doctest improvements:
- Convert complete MySoC examples to testcode blocks with assertions
- Two examples converted: using-pin-signatures.rst and architecture.rst
- Examples now validate that classes can be instantiated correctly
- All doctests pass (3 tests total)

Strategy: Convert only complete, self-contained examples that use documented
public APIs. Keep illustrative fragments as code-block for readability.

🤖 Generated with [Claude Code](https://claude.com/claude-code)

Co-Authored-By: Claude <noreply@anthropic.com>

Author: robtaylor

docs/architecture.rst

@@ -58,13 +58,9 @@ Design Flow in Detail
 
 You write your design in Python using Amaranth HDL and ChipFlow signatures:
 
-.. code-block:: python
-
-    from chipflow_lib.platforms import UARTSignature, GPIOSignature
-    from amaranth import Module
-    from amaranth.lib.wiring import Component, Out
+.. testcode::
 
-    class MySoC(Component):
+    class MySoC(wiring.Component):
         def __init__(self):
             super().__init__({
                 "uart": Out(UARTSignature()),
@@ -76,6 +72,11 @@ You write your design in Python using Amaranth HDL and ChipFlow signatures:
             # Your design logic here
             return m
 
+    # Verify the design can be instantiated
+    design = MySoC()
+    assert hasattr(design, 'uart')
+    assert hasattr(design, 'gpio')
+
 2. Signatures Add Metadata
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~
 

docs/using-pin-signatures.rst

@@ -34,11 +34,9 @@ Using Pin Signatures in Your Top-Level Design
 
 Pin signatures are used when defining your top-level component's interface:
 
-.. code-block:: python
-
-    from amaranth.lib.wiring import Out
-    from chipflow_lib.platforms import UARTSignature, GPIOSignature, QSPIFlashSignature
+.. testcode::
 
+    # Define a simple SoC with external interfaces
     class MySoC(wiring.Component):
         def __init__(self):
             super().__init__({
@@ -47,6 +45,12 @@ Pin signatures are used when defining your top-level component's interface:
                 "flash": Out(QSPIFlashSignature()),
             })
 
+    # Verify the component can be instantiated
+    soc = MySoC()
+    assert hasattr(soc, 'uart')
+    assert hasattr(soc, 'gpio')
+    assert hasattr(soc, 'flash')
+
 These signatures tell ChipFlow:
 
 - How to connect your design to the physical pins of your chip