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4 files changed

+40
-70
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chipflow_lib/pin_lock.py

Lines changed: 2 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -2,19 +2,12 @@
22
import inspect
33
import logging
44

5-
from pprint import pformat
65
from pathlib import Path
7-
from typing import Any, List, Dict, Tuple
86

9-
from chipflow_lib import _parse_config, _ensure_chipflow_root, ChipFlowError
7+
from chipflow_lib import _parse_config, _ensure_chipflow_root
108
from chipflow_lib.platforms import (
11-
PACKAGE_DEFINITIONS,
12-
PIN_ANNOTATION_SCHEMA,
139
top_components,
14-
LockFile,
15-
Package,
16-
PortMap,
17-
Port
10+
LockFile
1811
)
1912
from chipflow_lib.config_models import Config
2013

chipflow_lib/platforms/utils.py

Lines changed: 38 additions & 59 deletions
Original file line numberDiff line numberDiff line change
@@ -5,8 +5,9 @@
55
import pydantic
66

77
from collections import OrderedDict, deque
8-
from collections.abc import MutableMapping
8+
from collections.abc import MutableMapping, Sequence
99
from enum import Enum, IntEnum, StrEnum, auto
10+
from math import ceil, floor
1011
from pprint import pformat
1112
from typing import Any, Dict, List, Set, Tuple, Optional, Union, Literal
1213

@@ -580,7 +581,7 @@ def bringup_pins(self) -> BringupPins:
580581

581582

582583
def _allocate(self, available: PinSet, width: int) -> PinList:
583-
avail_n = self.sortpins(available)
584+
avail_n = self._sortpins(available)
584585
logger.debug(f"BareDiePackageDef.allocate {width} from {len(avail_n)} remaining")
585586
ret = _find_contiguous_sequence(self._ordered_pins, avail_n, width)
586587
logger.debug(f"BareDiePackageDef.returned {ret}")
@@ -646,9 +647,6 @@ def _allocate(self, available: Set[str], width: int) -> List[str]:
646647
assert len(ret) == width
647648
return ret
648649

649-
def sortpins(self, pins: Union[List[str], Set[str]]) -> List[str]:
650-
return sorted(list(pins), key=int)
651-
652650
@property
653651
def bringup_pins(self) -> BringupPins:
654652
return BringupPins(
@@ -774,83 +772,64 @@ class GAPackageDef(BasePackageDef):
774772
additional_pins: Optional[Set[GAPin]]
775773

776774
def model_post_init(self, __context):
775+
def int_to_alpha(i: int):
776+
while i > 0:
777+
char = i % 26
778+
i = i // 26
779+
out = chr(ord('A')+char-1) + out
780+
return out
781+
782+
def pins_for_range(h1, h2, w1, w2):
783+
return set([[(int_to_alpha(h),w) for h in range(h1, h2)] for w in range(w1, w2)])
784+
777785
match self.layout_type:
778786
case GALayout.FULL:
779-
pins = ([(chr(h),w) for h in range(ord('a'), ord('a') + self.height + 10 )])
787+
pins = pins_for_range(1, self.height, 1, self.width)
788+
780789
case GALayout.PERIMETER:
781-
pins = set([str(i) for i in range(8, self.width * 2 + self.height * 2)] - )
782-
case GALayout.CHANNEL:
790+
pins = pins_for_range(1, self.height, 1, self.width) - \
791+
pins_for_range(1 + self.channel_width, self.height-self.channel_width, 1 + self.channel_width, self.width - self.channel_width)
792+
783793
case GALayout.ISLAND:
794+
pins = pins_for_range(1, self.height, 1, self.width) - \
795+
pins_for_range(1 + self.channel_width, self.height-self.channel_width, 1 + self.channel_width, self.width - self.channel_width) + \
796+
pins_for_range(ceil(self.height/ 2 - self.island_width /2), floor(self.height/2 + self.island_width /2),
797+
ceil(self.width / 2 - self.island_width /2), floor(self.width /2 + self.island_width /2))
798+
799+
case GALayout.CHANNEL:
800+
pins = pins_for_range(1, self.channel_width + 1, 1, self.width) + \
801+
pins_for_range(self.height - self.channel_width, self.height, 1, self.width)
784802

785-
pins =(
786-
set([str(i) for i in range(8, self.width * 2 + self.height * 2)])
787-
- set(self.power.values())
788-
- set(self.power.clocks.values())
789-
- set(self.power.jtag.values())
790-
)
791803
self._ordered_pins = sorted(pins)
792804
return super().model_post_init(__context)
793805

794806

795-
def allocate(self, available: Set[str], width: int) -> List[str]:
807+
def _allocate(self, available: Set[str], width: int) -> List[str]:
796808
avail_n = sorted(available)
797809
logger.debug(f"GAPackageDef.allocate {width} from {len(avail_n)} remaining: {available}")
798810
ret = _find_contiguous_sequence(self._ordered_pins, avail_n, width)
799811
logger.debug(f"GAPackageDef.returned {ret}")
800812
assert len(ret) == width
801813
return ret
802814

803-
def sortpins(self, pins: Union[List[str], Set[str]]) -> List[str]:
804-
return sorted(list(pins), key=int)
805-
806815
@property
807-
def power(self) -> List[Tuple[Pin, Pin]]:
808-
"""
809-
The set of power pins for a quad package.
810-
Power pins are always a matched pair in the middle of a side, with the number
811-
varying with the size of the package.
812-
We don't move power pins from these locations to allow for easier bring up test.
813-
"""
814-
pins = []
815-
n = (self.width + self.height)//12
816-
# Left
817-
pins.append((str(self.height//2), str(self.height//2 +1)))
818-
# Bottom
819-
start = self.height
820-
if n > 2:
821-
pins.append((str(start + self.width//2), str(start + self.width//2 +1)))
822-
# Right
823-
start = start + self.width
824-
if n > 1:
825-
pins.append((str(start + self.height//2), str(start + self.height//2 +1)))
826-
# Top
827-
start = start + self.height
828-
if n > 3:
829-
pins.append((str(start + self.width//2), str(start + self.width//2 +1)))
830-
return pins
831-
816+
def bringup_pins(self) -> BringupPins:
817+
return BringupPins(
818+
core_power=[self._power],
819+
core_clock={0: str(2)},
820+
core_reset={0: str(1)},
821+
core_heartbeat={0: str(self.width * 2 + self.height * 2 - 1)},
822+
core_jtag=self._jtag
823+
)
832824

833825

834826
@property
835-
def resets(self) -> Dict[int, Pin]:
836-
"""
837-
Numbered set of reset pins for the package
838-
Default implementation with one reset pin
839-
near the beginning of the package
840-
"""
841-
return {0: str(1)} # Second pin
827+
def _power(self) -> List[PowerPins]:
828+
return [PowerPins(1,2)]
842829

843-
@property
844-
def clocks(self) -> Dict[int, Pin]:
845-
"""
846-
Numbered set of clock pins for the package
847-
Default implementation with one clock pin
848-
near the beginning of the package
849-
"""
850-
return {0: str(2)} # Third pin
851830

852831
@property
853-
def jtag(self) -> Dict[JTAGWire, Pin]:
832+
def _jtag(self) -> Dict[JTAGWire, Pin]:
854833
"""
855834
Map of JTAG pins for the package
856835
"""

tests/test_package_pins.py

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,5 @@
11
# SPDX-License-Identifier: BSD-2-Clause
22
import unittest
3-
from unittest import mock
43

54
from chipflow_lib.platforms.utils import (
65
_BareDiePackageDef, _PGAPackageDef,

tests/test_utils_additional.py

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,6 @@
1414
PIN_ANNOTATION_SCHEMA,
1515
IOSignature,
1616
_Side,
17-
_BasePackageDef,
1817
_BareDiePackageDef,
1918
_PGAPackageDef,
2019
Package,

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