wip - need to coalesce interface power pins

Author: robtaylor

chipflow_lib/_config_models.py

@@ -14,6 +14,8 @@ class SiliconConfig(BaseModel):
     power: Dict[str, Voltage] = {}
     debug: Optional[Dict[str, bool]] = None
 
+# TODO: add validation that top components, clock domains and power domains
+#       not begin with '_' (unless power domain _core)
 class ChipFlowConfig(BaseModel):
     """Root configuration for chipflow.toml."""
     project_name: str

chipflow_lib/platforms/_utils.py

@@ -70,7 +70,7 @@ def build(self, e):
             print("write_cxxrtl -header sim_soc.cc", file=yosys_file)
 
     def instantiate_ports(self, m: Module):
-        if hasattr(self, "_pinlock"):
+        if self._pinlock:  # already instantiated
             return
 
         pinlock = load_pinlock()
@@ -94,7 +94,7 @@ def instantiate_ports(self, m: Module):
             assert 'clock_domain' in reset.iomodel
             domain = reset.iomodel['clock_domain']
             logger.debug(f"Instantiating reset synchronizer for {reset.port_name}, domain {domain}")
-            rst_buffer = io.Buffer(reset.direction, self._ports[clock.port_name])
+            rst_buffer = io.Buffer(reset.direction, self._ports[reset.port_name])
             setattr(m.submodules, reset.port_name, rst_buffer)
             ffsync = FFSynchronizer(rst_buffer.i, ResetSignal())  # type: ignore[reportAttributeAccessIssue]
             setattr(m.submodules, reset.port_name + "_sync", ffsync)

chipflow_lib/platforms/sim.py

@@ -53,6 +53,7 @@ def _wire_up_ports(m: Module, top, platform):
         print(">  {n}:{t}")
         setattr(m.submodules, n, t)
 
+    assert platform._pinlock
     for component, iface in platform._pinlock.port_map.ports.items():
         if component.startswith('_'):
             logger.debug(f"Ignoring special component {component}")

chipflow_lib/steps/__init__.py

@@ -243,6 +243,7 @@ def network_err(e):
                 exit(2)
 
     def _long_poll_stream(self, sp, network_err):
+        assert self._log_stream_url
         steps = self._last_log_steps
         stream_event_counter = 0
         assert self._chipflow_api_key
@@ -305,7 +306,10 @@ def _stream_logs(self, sp, network_err):
         build_status = "pending"
         stream_event_counter = 0
         self._last_log_steps = []
-        assert self._chipflow_api_key is not None
+
+        assert self._chipflow_api_key
+        assert self._build_status_url
+
         while fail_counter < 10 and stream_event_counter < 10:
             sp.text = f"Waiting for build to run... {build_status}"
             time.sleep(timeout)  # Wait before polling

chipflow_lib/steps/silicon.py

@@ -89,8 +89,12 @@ def build(self, *args):
         #    m.d.sync += heartbeat_ctr.eq(heartbeat_ctr + 1)
         #    m.d.comb += platform.request("heartbeat").o.eq(heartbeat_ctr[-1])
 
+        assert self._platform._pinlock
+
         top = top_components(self._config)
         logger.debug(f"SimStep top = {top}")
+        logger.debug(f"port map ports =\n{pformat(self._platform._pinlock.port_map.ports)}")
+
 
         _wire_up_ports(m, top, self._platform)
 

chipflow_lib/steps/sim.py

@@ -19,7 +19,7 @@ Each package type (PGA, bare die, etc.) defines its own implementation of these
 ### Getting Default Pins
 
 ```python
-from chipflow_lib.platforms._ import PACKAGE_DEFINITIONS, PowerType, JTAGWireName
+from chipflow_lib.platforms._utils import PACKAGE_DEFINITIONS, PowerType, JTAGWireName
 
 # Get a package definition
 package_def = PACKAGE_DEFINITIONS["pga144"]
@@ -42,7 +42,7 @@ tms_pin = jtag_pins[JTAGWireName.TMS]  # Get the TMS pin
 ### Creating a Package with Default Pins
 
 ```python
-from chipflow_lib.platforms._ import PACKAGE_DEFINITIONS
+from chipflow_lib.platforms._utils import PACKAGE_DEFINITIONS
 
 # Create a package with a specific package definition
 package = Package(package_type=PACKAGE_DEFINITIONS["pga144"])

docs/package_pins.md

@@ -2,8 +2,6 @@
 import os
 import unittest
 
-from chipflow_lib._config_models import PadConfig
-
 
 class ConfigModelsTestCase(unittest.TestCase):
     def setUp(self):
@@ -36,16 +34,6 @@ def test_config_validation(self):
         # self.assertEqual(config.chipflow.silicon.process, Process.SKY130)
         self.skipTest("Config validation temporarily disabled")
 
-    def test_pad_config(self):
-        """Test validation of pad configuration."""
-        pad = PadConfig(type="clock", loc="114")
-        self.assertEqual(pad.type, "clock")
-        self.assertEqual(pad.loc, "114")
-
-        # Test validation of loc format
-        with self.assertRaises(ValueError):
-            PadConfig(type="clock", loc="invalid-format")
-
     def test_nested_structure(self):
         """Test the nested structure of the Config model."""
         # Temporarily disabled due to power config validation issues

tests/test_config_models.py

@@ -1,8 +1,8 @@
 # SPDX-License-Identifier: BSD-2-Clause
 import unittest
 
-from chipflow_lib.platforms._ import (
-    BareDiePackageDef, QuadPackageDef, Package, GAPackageDef, GALayout, GAPin
+from chipflow_lib.platforms import (
+    BareDiePackageDef, QuadPackageDef, GAPackageDef
 )
 
 
@@ -74,56 +74,11 @@ def test_bringup_pins(self):
         self.assertIsNotNone(jtag.tdo)
 
 
-class TestPackage(unittest.TestCase):
-    def setUp(self):
-        self.package_def = BareDiePackageDef(name="test_package", width=8, height=4)
-        self.package = Package(type=self.package_def)
-
-    def test_package_initialization(self):
-        """Test basic package initialization"""
-        self.assertIsNotNone(self.package.type)
-        self.assertEqual(self.package.type.name, "test_package")
-        self.assertEqual(self.package.type.width, 8)
-        self.assertEqual(self.package.type.height, 4)
-
-    def test_package_type_access(self):
-        """Test accessing package type properties through Package"""
-        # Should be able to access package type bringup pins
-        bringup_pins = self.package.type.bringup_pins
-        self.assertIsNotNone(bringup_pins)
-
-        # Test package discriminator
-        self.assertEqual(self.package.type.package_type, "BareDiePackageDef")
-
-
 class TestGAPackage(unittest.TestCase):
-    def test_gapin_creation(self):
-        """Test GAPin creation and equality"""
-        pin1 = GAPin(h="A", w=1)
-        pin2 = GAPin(h="A", w=1)
-        pin3 = GAPin(h="B", w=2)
-
-        # Test equality
-        self.assertEqual(pin1, pin2)
-        self.assertNotEqual(pin1, pin3)
-
-        # Test attributes
-        self.assertEqual(pin1.h, "A")
-        self.assertEqual(pin1.w, 1)
-        self.assertEqual(pin3.h, "B")
-        self.assertEqual(pin3.w, 2)
-
-    def test_galayout_enum_values(self):
-        """Test GALayout enum values"""
-        self.assertEqual(GALayout.FULL, "full")
-        self.assertEqual(GALayout.PERIMETER, "perimeter")
-        self.assertEqual(GALayout.CHANNEL, "channel")
-        self.assertEqual(GALayout.ISLAND, "island")
-
     def test_gapackagedef_class_structure(self):
         """Test GAPackageDef class structure and type"""
         # Test that we can import and access the class
-        from chipflow_lib.platforms._ import BasePackageDef
+        from chipflow_lib.platforms._utils import BasePackageDef
 
         # Test that GAPackageDef inherits from BasePackageDef
         self.assertTrue(issubclass(GAPackageDef, BasePackageDef))
@@ -155,90 +110,15 @@ def test_gapackagedef_pydantic_model(self):
         # Test that it has the expected type field in model_fields
         self.assertIn('package_type', GAPackageDef.model_fields)
 
-    def test_missing_pins_configuration(self):
-        """Test missing pins configuration"""
-        # Since GAPin is not hashable, test individual pins
-        pin1 = GAPin(h="A", w=1)
-        pin2 = GAPin(h="B", w=2)
-        pin3 = GAPin(h="C", w=3)
-
-        # Test that pins can be created correctly
-        self.assertEqual(pin1.h, "A")
-        self.assertEqual(pin1.w, 1)
-        self.assertEqual(pin2.h, "B")
-        self.assertEqual(pin2.w, 2)
-        self.assertEqual(pin3.h, "C")
-        self.assertEqual(pin3.w, 3)
-
-        # Test that pins are equal to themselves
-        self.assertEqual(pin1, GAPin(h="A", w=1))
-        self.assertEqual(pin2, GAPin(h="B", w=2))
-
-    def test_additional_pins_configuration(self):
-        """Test additional pins configuration"""
-        # Since GAPin is not hashable, test individual pins
-        pin1 = GAPin(h="D", w=4)
-        pin2 = GAPin(h="E", w=5)
-
-        # Test that additional pins can be created correctly
-        self.assertEqual(pin1.h, "D")
-        self.assertEqual(pin1.w, 4)
-        self.assertEqual(pin2.h, "E")
-        self.assertEqual(pin2.w, 5)
-
-        # Test equality
-        self.assertEqual(pin1, GAPin(h="D", w=4))
-        self.assertEqual(pin2, GAPin(h="E", w=5))
-
-    def test_layout_type_values(self):
-        """Test different layout type values"""
-        # Test that GALayout values are correct
-        self.assertEqual(GALayout.FULL.value, "full")
-        self.assertEqual(GALayout.PERIMETER.value, "perimeter")
-        self.assertEqual(GALayout.CHANNEL.value, "channel")
-        self.assertEqual(GALayout.ISLAND.value, "island")
-
     def test_package_public_api_methods(self):
         """Test that expected public API methods exist"""
 
         # Test that expected methods exist
-        self.assertTrue(hasattr(GAPackageDef, 'allocate_pins'))
         self.assertTrue(hasattr(GAPackageDef, 'bringup_pins'))
-        self.assertTrue(hasattr(GAPackageDef, 'heartbeat'))
-        self.assertTrue(hasattr(GAPackageDef, '_power'))
-        self.assertTrue(hasattr(GAPackageDef, '_jtag'))
-
-        # Test that these are callable or properties
-        self.assertTrue(callable(GAPackageDef.allocate_pins))
-        # bringup_pins, heartbeat, _power, _jtag are properties
-
-    def test_gapin_equality_operations(self):
-        """Test that GAPin equality works correctly"""
-        pin1 = GAPin(h="A", w=1)
-        pin2 = GAPin(h="A", w=1)  # Duplicate
-        pin3 = GAPin(h="B", w=2)
-
-        # Test that GAPin equality works correctly
-        self.assertEqual(pin1, pin2)  # pin1 and pin2 are equal
-        self.assertNotEqual(pin1, pin3)  # pin1 and pin3 are different
-        self.assertNotEqual(pin2, pin3)  # pin2 and pin3 are different
-
-        # Test that different coordinates create different pins
-        self.assertNotEqual(GAPin(h="A", w=1), GAPin(h="A", w=2))
-        self.assertNotEqual(GAPin(h="A", w=1), GAPin(h="B", w=1))
-
-    def test_gapin_string_representation(self):
-        """Test GAPin string representation"""
-        pin = GAPin(h="A", w=1)
-
-        # Test that pin has reasonable string representation
-        str_repr = str(pin)
-        self.assertIn("A", str_repr)
-        self.assertIn("1", str_repr)
 
     def test_inheritance_from_basepackagedef(self):
         """Test that GAPackageDef properly inherits from BasePackageDef"""
-        from chipflow_lib.platforms._ import BasePackageDef
+        from chipflow_lib.platforms._utils import BasePackageDef
 
         # Test inheritance
         self.assertTrue(issubclass(GAPackageDef, BasePackageDef))

tests/test_package_pins.py

@@ -7,7 +7,7 @@
 from amaranth.lib import io
 
 from chipflow_lib import ChipFlowError
-from chipflow_lib.platforms._ import (
+from chipflow_lib.platforms._utils import (
     IOModel,
     Port,
     PortMap,
@@ -28,13 +28,13 @@ def __init__(self, name="test_package"):
         self._components = {}
         # Create mocks for the methods
         self.register_component = mock.MagicMock(side_effect=self._register_component)
-        self.allocate_pins = mock.MagicMock()
-        self.allocate = mock.MagicMock(side_effect=self._allocate)
+        self._allocate_pins = mock.MagicMock()
+        self._allocate = mock.MagicMock(side_effect=self._allocate)
         self.bringup_pins = mock.PropertyMock()
 
         # Setup allocate_pins to return a mock LockFile
         mock_lockfile = mock.MagicMock()
-        self.allocate_pins.return_value = mock_lockfile
+        self._allocate_pins.return_value = mock_lockfile
 
     def _register_component(self, name, component):
         """Mock implementation of register_component"""
@@ -199,7 +199,7 @@ def test_lock_pins_new_lockfile(self, mock_lock_file, mock_package_defs,
 
         # Verify the package definition was used
         mock_package_type.register_component.assert_called()
-        mock_package_type.allocate_pins.assert_called()
+        mock_package_type._allocate_pins.assert_called()
 
         # Verify write was called with the JSON data
         file_handle = mock_open.return_value.__enter__.return_value