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Updated based on PR #144 review feedback:
1. Expanded explanation of what pin signatures tell ChipFlow:
- Physical pin connections
- Simulation model and test bench selection
- Pad and package pin allocation requirements
2. Added comprehensive IOModelOptions documentation:
- Full reference of all available options
- Examples showing basic and advanced usage
- Details on invert, individual_oe, power_domain, clock_domain
- Trip point options (CMOS, TTL, VCORE, VREF, SCHMITT_TRIGGER)
- Buffer control and initialization options
This provides users with complete understanding of how to configure
pin electrical and behavioral properties.
- **invert** (``bool`` or ``Tuple[bool, ...]``) - Polarity inversion for pins. Can be a single bool for all pins or a tuple specifying inversion per pin.
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- **individual_oe** (``bool``) - If ``True``, each output wire has its own Output Enable bit. If ``False`` (default), a single OE bit controls the entire port.
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- **power_domain** (``str``) - Name of the I/O power domain. Pins with different power domains must be in separate signatures.
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- **clock_domain** (``str``) - Name of the I/O's clock domain (default: ``'sync'``). Pins with different clock domains must be in separate signatures.
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- **buffer_in** (``bool``) - Enable input buffer on the I/O pad.
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- **buffer_out** (``bool``) - Enable output buffer on the I/O pad.
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- **sky130_drive_mode** (:class:`Sky130DriveMode`) - Drive mode for Sky130 output buffers (see below).
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- **trip_point** (:class:`IOTripPoint`) - Input buffer trip point configuration:
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- ``IOTripPoint.CMOS`` - CMOS switching levels (30%/70%) referenced to I/O power domain
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