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Address PR review comments: expand pin signatures documentation
Updated based on PR #144 review feedback: 1. Expanded explanation of what pin signatures tell ChipFlow: - Physical pin connections - Simulation model and test bench selection - Pad and package pin allocation requirements 2. Added comprehensive IOModelOptions documentation: - Full reference of all available options - Examples showing basic and advanced usage - Details on invert, individual_oe, power_domain, clock_domain - Trip point options (CMOS, TTL, VCORE, VREF, SCHMITT_TRIGGER) - Buffer control and initialization options This provides users with complete understanding of how to configure pin electrical and behavioral properties.
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docs/using-pin-signatures.rst

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@@ -27,9 +27,7 @@ Available Pin Signatures
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- ``QSPIFlashSignature()`` - Quad SPI flash interface
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- ``JTAGSignature()`` - JTAG debug interface
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All pin signatures support additional options:
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- ``sky130_drive_mode`` - Set drive strength for Sky130 (e.g., ``Sky130DriveMode.OPEN_DRAIN_STRONG_UP``)
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All pin signatures accept ``IOModelOptions`` to customize their electrical and behavioral properties (see below).
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Using Pin Signatures in Your Top-Level Design
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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"flash": Out(QSPIFlashSignature()),
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})
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These signatures tell ChipFlow how to connect your design to the physical pins of your chip.
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These signatures tell ChipFlow:
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- How to connect your design to the physical pins of your chip
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- How to select appropriate simulation models and test benches for each interface
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- Requirements for pad and package pin allocation (power domains, drive strength, etc.)
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IO Model Options
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~~~~~~~~~~~~~~~~
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All pin signatures accept ``IOModelOptions`` to configure the electrical and behavioral properties of the I/O pins:
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.. code-block:: python
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from chipflow_lib.platforms import GPIOSignature, IOTripPoint
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super().__init__({
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# Basic GPIO
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"gpio_basic": Out(GPIOSignature(pin_count=4)),
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# GPIO with custom options
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"gpio_custom": Out(GPIOSignature(
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pin_count=8,
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invert=True, # Invert all pins
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individual_oe=True, # Separate OE for each pin
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clock_domain='io_clk', # Use IO clock domain
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trip_point=IOTripPoint.TTL, # TTL input thresholds
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init=0x00, # Initial output values
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init_oe=0xFF # Initial OE values (all enabled)
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))
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})
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Available IOModelOptions
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^^^^^^^^^^^^^^^^^^^^^^^^
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- **invert** (``bool`` or ``Tuple[bool, ...]``) - Polarity inversion for pins. Can be a single bool for all pins or a tuple specifying inversion per pin.
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- **individual_oe** (``bool``) - If ``True``, each output wire has its own Output Enable bit. If ``False`` (default), a single OE bit controls the entire port.
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- **power_domain** (``str``) - Name of the I/O power domain. Pins with different power domains must be in separate signatures.
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- **clock_domain** (``str``) - Name of the I/O's clock domain (default: ``'sync'``). Pins with different clock domains must be in separate signatures.
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- **buffer_in** (``bool``) - Enable input buffer on the I/O pad.
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- **buffer_out** (``bool``) - Enable output buffer on the I/O pad.
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- **sky130_drive_mode** (:class:`Sky130DriveMode`) - Drive mode for Sky130 output buffers (see below).
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- **trip_point** (:class:`IOTripPoint`) - Input buffer trip point configuration:
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- ``IOTripPoint.CMOS`` - CMOS switching levels (30%/70%) referenced to I/O power domain
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- ``IOTripPoint.TTL`` - TTL levels (low < 0.8V, high > 2.0V)
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- ``IOTripPoint.VCORE`` - CMOS levels referenced to core power domain
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- ``IOTripPoint.VREF`` - CMOS levels referenced to external reference voltage
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- ``IOTripPoint.SCHMITT_TRIGGER`` - Schmitt trigger for noise immunity
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- **init** (``int`` or ``bool``) - Initial values for output signals.
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- **init_oe** (``int`` or ``bool``) - Initial values for output enable signals.
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Sky130-Specific Pin Configuration
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

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