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1 parent 1161e9e commit 172215eCopy full SHA for 172215e
chipflow_lib/providers/board_ulx3s.py
@@ -79,7 +79,7 @@ def __init__(self):
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def elaborate(self, platform):
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m = Module()
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- uart_pins = platform.request("uart", 0, dir={"rx": "-", "tx": "-"})
+ uart_pins = platform.request("uart", 0, dir=dict(rx="-", tx="-", rts="-", dtr="-"))
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m.submodules.uart_rx = uart_rx = io.Buffer("i", uart_pins.rx)
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m.submodules.uart_tx = uart_tx = io.Buffer("o", uart_pins.tx)
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m.d.comb += [
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