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Fixes for test suite
1 parent e24f36e commit 13ea54b

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3 files changed

+4
-51
lines changed

3 files changed

+4
-51
lines changed

tests/fixtures/mock.toml

Lines changed: 0 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -7,19 +7,3 @@ silicon = "chipflow_lib.steps.silicon:SiliconStep"
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[chipflow.silicon]
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process = "ihp_sg13g2"
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package = "pga144"
10-
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[chipflow.clocks]
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default = 'sys_clk'
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[chipflow.resets]
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default = 'sys_rst_n'
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[chipflow.silicon.pads]
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sys_clk = { type = "clk", loc = "N3" }
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sys_rst_n = { type = "i", loc = "N4" }
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[chipflow.silicon.power]
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vss = { loc = "N1" }
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vssio = { loc = "N5" }
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vddio = { loc = "N6" }
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vdd = { loc = "N7" }

tests/test_init.py

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -94,8 +94,6 @@ def test_parse_config_file_valid(self):
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[chipflow]
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project_name = "test_project"
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steps = { silicon = "chipflow_lib.steps.silicon:SiliconStep" }
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clocks = { default = "sys_clk" }
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resets = { default = "sys_rst_n" }
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[chipflow.silicon]
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process = "sky130"

tests/test_steps_silicon.py

Lines changed: 4 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -22,11 +22,12 @@
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from chipflow_lib.cli import run as cli_run
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from chipflow_lib.steps.silicon import SiliconStep, SiliconTop
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from chipflow_lib.config_models import Config, ChipFlowConfig, SiliconConfig
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from chipflow_lib.platforms._internal import Process
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DEFAULT_PINLOCK = {
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"process" : "ihp_sg13g2",
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"package" : {
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"type": {
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"package_type": {
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"name": "pga144",
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"package_type": "QuadPackageDef",
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"width": 36,
@@ -56,7 +57,7 @@ def setUp(self):
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os.environ, {"CHIPFLOW_ROOT": self.temp_dir.name}
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)
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self.chipflow_root_patcher.start()
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_ensure_chipflow_root.root = None
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_ensure_chipflow_root.root = None # type: ignore
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# Create basic config for tests
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self.config = {
@@ -97,9 +98,8 @@ def test_init(self, mock_silicontop_class):
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top={"mock_component": "module.MockComponent"},
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silicon=SiliconConfig(
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package="cf20",
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process="ihp_sg13g2",
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process=Process.HELVELLYN2,
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debug={"heartbeat": True},
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pads={},
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power={}
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)
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))
@@ -133,7 +133,6 @@ def test_prepare(self, mock_top_components, mock_platform_class, mock_silicontop
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package="cf20",
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process="ihp_sg13g2",
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debug={"heartbeat": True},
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pads={},
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power={}
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)
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))
@@ -182,34 +181,6 @@ def test_build_cli_parser(self):
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default=False, action="store_true"
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)
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@mock.patch("chipflow_lib.steps.silicon.SiliconPlatform")
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@mock.patch("chipflow_lib.steps.silicon.top_components")
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@mock.patch("chipflow_lib.steps.silicon.dotenv.load_dotenv")
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@mock.patch("chipflow_lib.steps.silicon.SiliconStep.submit")
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@mock.patch("chipflow_lib.steps.silicon.SiliconStep.prepare")
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def test_cli_prepare(self, mock_prepare, mock_submit, mock_dotenv, mock_top_components, mock_platform_class):
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"""Test prepare method"""
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mock_platform = mock_platform_class.return_value
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mock_platform.build.return_value = "/path/to/rtlil"
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# Create mock args
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args = mock.MagicMock()
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args.action = "prepare"
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# Create SiliconStep instance - parse config first
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config_obj = Config.model_validate(self.config)
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step = SiliconStep(config_obj)
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# Set up the mock to handle SiliconTop
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# Call the method
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step.run_cli(args)
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mock_prepare.assert_called_once()
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mock_submit.assert_not_called()
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# Verify dotenv not loaded for prepare
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mock_dotenv.assert_not_called()
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213184
@unittest.skip
214185
@mock.patch("chipflow_lib.steps.silicon.SiliconTop")
215186
@mock.patch("chipflow_lib.steps.silicon.SiliconStep.prepare")

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