Rename PinSignature to IOSignature\n\nAvoids clash with amaranth-soc entity of same name

Author: robtaylor

amaranth_orchard/io/gpio.py

@@ -4,7 +4,7 @@
 
 from amaranth_soc import csr, gpio
 
-from chipflow_lib.platforms import BidirPinSignature
+from chipflow_lib.platforms import BidirIOSignature
 
 __all__ = ["GPIOPeripheral"]
 
@@ -17,14 +17,14 @@ def __init__(self, pin_count=1):
                 raise ValueError(f"Pin pin_count must be lesser than or equal to 32, not {pin_count}")
             self._pin_count = pin_count
             super().__init__({
-                "gpio": Out(BidirPinSignature(pin_count, all_have_oe=True))
+                "gpio": Out(BidirIOSignature(pin_count, all_have_oe=True))
                 })
 
         @property
         def pin_count(self):
             return self._pin_count
 
-    """Wrapper for amaranth_soc gpio with chipflow_lib.PinSignature support
+    """Wrapper for amaranth_soc gpio with chipflow_lib.IOSignature support
 
     Parameters
     ----------
@@ -42,7 +42,7 @@ def pin_count(self):
     ----------
     bus : :class:`csr.Interface`
         CSR bus interface providing access to registers.
-    pins : :class:`list` of :class:`wiring.PureInterface` of :class:`PinSignature`
+    pins : :class:`list` of :class:`wiring.PureInterface` of :class:`IOSignature`
         GPIO pin interfaces.
     alt_mode : :class:`Signal`
         Indicates which members of the :attr:`Peripheral.pins` array are in alternate mode.

amaranth_orchard/io/i2c.py

@@ -3,14 +3,14 @@
 from amaranth.lib.wiring import In, Out, connect, flipped
 
 from amaranth_soc import csr
-from chipflow_lib.platforms import BidirPinSignature
+from chipflow_lib.platforms import BidirIOSignature
 from .glasgow_i2c import I2CInitiator
 
 __all__ = ["I2CPeripheral", "I2CSignature"]
 
 I2CSignature = wiring.Signature({
-    "scl": Out(BidirPinSignature(1)),
-    "sda": Out(BidirPinSignature(1))
+    "scl": Out(BidirIOSignature(1)),
+    "sda": Out(BidirIOSignature(1))
     })
 
 

amaranth_orchard/io/spi.py

@@ -3,15 +3,15 @@
 from amaranth.lib.wiring import In, Out, connect, flipped
 
 from amaranth_soc import csr
-from chipflow_lib.platforms import InputPinSignature, OutputPinSignature
+from chipflow_lib.platforms import InputIOSignature, OutputIOSignature
 
 __all__ = ["SPISignature", "SPIPeripheral"]
 
 SPISignature = wiring.Signature({
-    "sck": Out(OutputPinSignature(1)),
-    "copi": Out(OutputPinSignature(1)),
-    "cipo": Out(InputPinSignature(1)),
-    "csn": Out(OutputPinSignature(1)),
+    "sck": Out(OutputIOSignature(1)),
+    "copi": Out(OutputIOSignature(1)),
+    "cipo": Out(InputIOSignature(1)),
+    "csn": Out(OutputIOSignature(1)),
 })
 
 class SPIController(wiring.Component):

amaranth_orchard/io/uart.py

@@ -5,7 +5,7 @@
 from amaranth_soc import csr
 from amaranth_stdio.serial import AsyncSerialRX, AsyncSerialTX
 
-from chipflow_lib.platforms import OutputPinSignature, InputPinSignature
+from chipflow_lib.platforms import OutputIOSignature, InputIOSignature
 
 from . import rfc_uart
 
@@ -123,12 +123,12 @@ class UARTPeripheral(wiring.Component):
     class Signature(wiring.Signature):
         def __init__(self):
             super().__init__({
-                "tx": Out(OutputPinSignature(1)),
-                "rx": Out(InputPinSignature(1)),
+                "tx": Out(OutputIOSignature(1)),
+                "rx": Out(InputIOSignature(1)),
             })
 
 
-    """Wrapper for amaranth_soc RFC UART with PHY and chipflow_lib.PinSignature support
+    """Wrapper for amaranth_soc RFC UART with PHY and chipflow_lib.IOSignature support
 
     Parameters
     ----------
@@ -143,7 +143,7 @@ def __init__(self):
     ----------
     bus : :class:`csr.Interface`
         CSR bus interface providing access to registers.
-    pins : :class:`list` of :class:`wiring.PureInterface` of :class:`PinSignature`
+    pins : :class:`list` of :class:`wiring.PureInterface` of :class:`IOSignature`
         UART pin interfaces.
 
     """

amaranth_orchard/memory/hyperram.py

@@ -13,7 +13,7 @@
 from amaranth_soc import csr, wishbone
 from amaranth_soc.memory import MemoryMap
 
-from chipflow_lib.platforms import BidirPinSignature, OutputPinSignature
+from chipflow_lib.platforms import BidirIOSignature, OutputIOSignature
 
 __all__ = ["HyperRAM"]
 
@@ -22,11 +22,11 @@ class HyperRAM(wiring.Component):
     class Signature(wiring.Signature):
         def __init__(self, *, cs_count=1):
             super().__init__({
-                "clk": Out(OutputPinSignature(1)),
-                "csn": Out(OutputPinSignature(cs_count)),
-                "rstn": Out(OutputPinSignature(1)),
-                "rwds": Out(BidirPinSignature(1)),
-                "dq": Out(BidirPinSignature(8)),
+                "clk": Out(OutputIOSignature(1)),
+                "csn": Out(OutputIOSignature(cs_count)),
+                "rstn": Out(OutputIOSignature(1)),
+                "rwds": Out(BidirIOSignature(1)),
+                "dq": Out(BidirIOSignature(8)),
             })
 
     class CtrlConfig(csr.Register, access="rw"):

amaranth_orchard/memory/qspi_flash.py

@@ -9,7 +9,7 @@
 from amaranth_orchard.io.glasgow_iostream import PortGroup
 from amaranth_orchard.memory.glasgow_qspi import QSPIMode, QSPIController
 
-from chipflow_lib.platforms import BidirPinSignature, OutputPinSignature
+from chipflow_lib.platforms import BidirIOSignature, OutputIOSignature
 
 __all__ = ["QSPIFlash"]
 
@@ -252,9 +252,9 @@ class QSPIFlash(wiring.Component):
     class Signature(wiring.Signature):
         def __init__(self):
             super().__init__({
-                "clk": Out(OutputPinSignature(1)),
-                "csn": Out(OutputPinSignature(1)),
-                "d": Out(BidirPinSignature(4, all_have_oe=True)),
+                "clk": Out(OutputIOSignature(1)),
+                "csn": Out(OutputIOSignature(1)),
+                "d": Out(BidirIOSignature(4, all_have_oe=True)),
             })
 
     def __init__(self, *, addr_width, data_width):