wishbone: sram: allow SPRAM by disabling read port on write.

Author: kivikakk

amaranth_soc/wishbone/sram.py

@@ -106,6 +106,7 @@ def elaborate(self, platform):
         with m.Elif(self.wb_bus.cyc & self.wb_bus.stb):
             if self.writable:
                 m.d.comb += write_port.en.eq(Mux(self.wb_bus.we, self.wb_bus.sel, 0))
+                m.d.comb += read_port.en.eq(~self.wb_bus.we)
             m.d.sync += self.wb_bus.ack.eq(1)
 
         return m