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jakubcabaljakubcabal
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Merge branch 'cabal_fb2cdg1_prq' into 'devel'
feat(cards): add support for fb2cdg1 card with AGMF039R47A1E2VC See merge request ndk/ndk-fpga!317
2 parents 899dd36 + 9be68fc commit aa0d2d1

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‎apps/minimal/build/fb2cdg1/Makefile‎

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@@ -9,10 +9,13 @@ COMBO_BASE = ../../../..
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CARD_BASE = $(COMBO_BASE)/cards/silicom/fb2cdg1
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APP_CONF = app_conf.tcl
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BOARD_VARIANT ?= 1
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export BOARD_VARIANT
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PCIE_CONF ?= 1xgen5x8x8
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export PCIE_CONF
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OUTPUT_NAME = fb2cdg1-minimal-pcie$(PCIE_CONF)
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OUTPUT_NAME = fb2cdg1-var$(BOARD_VARIANT)-minimal-pcie$(PCIE_CONF)
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.PHONY: all 400g2
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‎apps/minimal/build/fb2cdg1/jenkins/var1-pcie1xgen5x16-400g2.jenkinsfile‎

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library 'liberouter'
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stagesFirmware(
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dir: 'apps/minimal/build/fb2cdg1',
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target: '400g2',
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tool: 'quartus',
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project: 'fb2cdg1-var1-minimal-pcie1xgen5x16-400g2',
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params: 'BOARD_VARIANT=1 PCIE_CONF=1xgen5x16',
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pollscm: 'H H(0-11) * * 6',
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rpms: false,
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rename: false,
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artifacts: 'fb2cdg1-var1-minimal-pcie1xgen5x16-400g2',
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lastBuilds: 2,
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)

‎apps/minimal/build/fb2cdg1/jenkins/var1-pcie1xgen5x8x8-400g2.jenkinsfile‎

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library 'liberouter'
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stagesFirmware(
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dir: 'apps/minimal/build/fb2cdg1',
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target: '400g2',
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tool: 'quartus',
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project: 'fb2cdg1-var1-minimal-pcie1xgen5x8x8-400g2',
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params: 'BOARD_VARIANT=1 PCIE_CONF=1xgen5x8x8',
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pollscm: 'H H(0-11) * * 6',
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rpms: false,
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rename: false,
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artifacts: 'fb2cdg1-var1-minimal-pcie1xgen5x8x8-400g2',
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lastBuilds: 2,
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)

‎cards/silicom/fb2cdg1/config/card_conf.tcl‎

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@@ -88,3 +88,4 @@ set MEM_PORTS 0
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# Other parameters:
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# ------------------------------------------------------------------------------
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set TSU_ENABLE true
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set BOARD_VARIANT $env(BOARD_VARIANT)

‎cards/silicom/fb2cdg1/config/card_const.tcl‎

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Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@
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# the description of this file, visit the Parametrization section in the
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# documentation of the NDK-CORE repostiory
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11-
set CARD_NAME "FB2CDG1"
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set CARD_NAME "FB2CDG1-VAR$BOARD_VARIANT"
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# Achitecture of Clock generator
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set CLOCK_GEN_ARCH "INTEL"
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# Achitecture of PCIe module

‎cards/silicom/fb2cdg1/constr/device.qsf‎ renamed to ‎cards/silicom/fb2cdg1/constr/device_var0.qsf‎

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Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
# device.qsf
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# device_var0.qsf
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# Copyright (C) 2025 DynaNIC Semiconductors, Ltd.
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# Author(s): David Beneš <benes@dyna-nic.com>
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#

‎cards/silicom/fb2cdg1/constr/device_var1.qsf‎

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@@ -0,0 +1,12 @@
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# device_var1.qsf
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# Copyright (C) 2025 CESNET
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# Author(s): Jakub Cabal <cabal@cesnet.cz>
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#
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# SPDX-License-Identifier: BSD-3-Clause
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# ==============================================================================
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# Global assignments
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# ==============================================================================
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set_global_assignment -name DEVICE AGMF039R47A1E2VC
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set_global_assignment -name FAMILY "Agilex 7"

‎cards/silicom/fb2cdg1/readme.rst‎

Lines changed: 65 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@ Silicom fb2CDg1\@AGM39D-2
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- PCIe conectors: Edge connector
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- `FPGA Card Website <https://www.silicom-usa.com/pr/server-adapters/programmable-fpga-server-adapter/fpga-intel-based-2/fpga-intel-agilex-based/fpga-smartnic-fb2cdg1agm39d-2-intel-based/>`_
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- FPGA specification:
13-
- FPGA part number: ``AGMF039R47A2E2VR0``
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- FPGA part number: ``AGMF039R47A2E2VR0``, ``AGMF039R47A1E2VC``
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- Ethernet Hard IP: F-Tile (up to 400G Ethernet)
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- PCIe Hard IP: R-Tile (up to PCIe Gen5 x16)
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@@ -30,3 +30,67 @@ NDK firmware support
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.. note::
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To build the NDK firmware for this card, you must have the Intel Quartus Prime Pro and PACSign tool installed, including a valid license.
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Board Variants
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^^^^^^^^^^^^^^
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This card exists in multiple variants.
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The correct variant for the firmware build can be selected using the Makefile parameter BOARD_VARIANT, for example as follows:
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.. code::
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$ cd <NDK-FPGA_root_directory>/apps/minimal/build/fb2cdg1
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$ make BOARD_VARIANT=1
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**Allowed values of BOARD_VARIANT parameter**
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- ``BOARD_VARIANT=1`` - The board uses FPGA part number ``AGMF039R47A1E2VC`` (Production sample).
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- ``BOARD_VARIANT=0`` - The board uses FPGA part number ``AGMF039R47A2E2VR0`` (Engineering sample).
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Initial Boot instructions
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^^^^^^^^^^^^^^^^^^^^^^^^^
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The card itself should be preloaded with firmware designed by Silicom.
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This design can be used to load an FPGA image to the BMC flash via PCIe using the Silicom ``rawcardtool`` tool.
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**Execute the following steps to perform the manual initialization:**
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1. Obtain PCIe address of the card by the command below. In this example, the PCIe address is ``01:00.0`` and will be used in the next steps:
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.. code::
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$ lspci | grep "Silicom Denmark Device"
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01:00.0 Ethernet controller: Silicom Denmark Device 0001
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2. Ensure the card respond to memory space accesses by command:
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.. code::
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$ setpci -s 01:00.0 COMMAND=0x0002
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3. Flash the ``fpga_page1_pacsign_user1.bin`` file to the card using RawCardTool provided by Silicom:
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.. code::
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$ rawcardtool_fjord --device 01:00.0 --flash fpga_page1_pacsign_user1.bin
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4. Set your design as default by command:
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.. code::
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$ rawcardtool_fjord --device 01:00.0 --fpgadefault user1
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5. Boot your design executing:
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.. code::
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$ rawcardtool_fjord --device 01:00.0 --reboot-fpga user1
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.. note::
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The ``fpga_page1_pacsign_user1.bin`` file will be located in the build folder of your application after building. For NDK-FPGA, the folder is ``ndk-fpga/apps/minimal/build/fb2cdg1``.
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.. note::
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If some bars are unmapped, power cycle the server.
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If the ``rawcardtool`` tool is unavailable, it is possible to use JTAG to load the design (SOF file), and ``nfb-boot`` command to load the BMC flash with the FPGA image:
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.. code::
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$ nfb-boot -f0 fb2cdg1-minimal-pcie1xgen5x8x8-400g2.nfw

‎cards/silicom/fb2cdg1/src/Quartus.inc.tcl‎

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Original file line numberDiff line numberDiff line change
@@ -24,7 +24,15 @@ set CARD_ARCHGRP(ETH_PORT_CHAN,0) $ETH_PORT_CHAN(0)
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set CARD_ARCHGRP(EHIP_PORT_TYPE,0) $EHIP_PORT_TYPE(0)
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# select fpga name
27-
set CARD_FPGA "AGMF039R47A2E2VR0"
27+
if {$BOARD_VARIANT == 0} {
28+
set CARD_FPGA "AGMF039R47A2E2VR0"
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} elseif {$BOARD_VARIANT == 1} {
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set CARD_FPGA "AGMF039R47A1E2VC"
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} else {
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error "Unsupported BOARD_VARIANT=$BOARD_VARIANT! Supported values are:
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- 0 for board with AGMF039R47A2E2VR0,
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- 1 for board with AGMF039R47A1E2VC."
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}
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set CARD_ARCHGRP(FPGA) $CARD_FPGA
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set CARD_ARCHGRP(BMC_CTRL_ARCH) "EMPTY"
@@ -58,7 +66,12 @@ set SYNTH_FLAGS(IP_FILES_CLEAN_ENABLE) 1
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#set SYNTH_FLAGS(CONSTR) ""
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set SYNTH_FLAGS(CONSTR) "$SYNTH_FLAGS(CONSTR) $CARD_BASE/constr/timing.sdc"
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set SYNTH_FLAGS(CONSTR) "$SYNTH_FLAGS(CONSTR) $CARD_BASE/constr/bmc.qsf"
61-
set SYNTH_FLAGS(CONSTR) "$SYNTH_FLAGS(CONSTR) $CARD_BASE/constr/device.qsf"
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if {$BOARD_VARIANT == 0} {
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lappend SYNTH_FLAGS(CONSTR) "$CARD_BASE/constr/device_var0.qsf"
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}
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if {$BOARD_VARIANT == 1} {
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lappend SYNTH_FLAGS(CONSTR) "$CARD_BASE/constr/device_var1.qsf"
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}
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set SYNTH_FLAGS(CONSTR) "$SYNTH_FLAGS(CONSTR) $CARD_BASE/constr/general.qsf"
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set SYNTH_FLAGS(CONSTR) "$SYNTH_FLAGS(CONSTR) $CARD_BASE/constr/qsfp_misc.qsf"
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set SYNTH_FLAGS(CONSTR) "$SYNTH_FLAGS(CONSTR) $CARD_BASE/constr/pcie.qsf"

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