Merge branch 'valek-feat-mfb_gen_status_reg_ext' into 'devel'

feat(mfb-generator-mi32): add DST_RDY to status signals

See merge request ndk/ndk-fpga!324

Author: jakubcabal

comp/mfb_tools/debug/generator/mfb_generator_mi32.vhd

@@ -334,7 +334,8 @@ begin
             MI_DRD <= (others => '0');
             case (MI_ADDR(6-1 downto 0)) is
                 when "000000"  => MI_DRD(0)                       <= en_reg;
-                    MI_DRD(1)                                     <= TX_MFB_SRC_RDY; -- read only busy bit
+                    MI_DRD(1)                                     <= TX_MFB_SRC_RDY;                     -- read only busy bit
+                    MI_DRD(2)                                     <= TX_MFB_DST_RDY;                     -- read only busy bit
                     MI_DRD(4)                                     <= clr_reg;
                 when "000100"  => MI_DRD(LENGTH_WIDTH-1 downto 0) <= len_reg;
                 when "001000"  => MI_DRD                          <= chan_inc_reg;

python/ofm/ofm/comp/mfb_tools/debug/generator/mfb_generator.py

@@ -76,6 +76,15 @@ def generating(self) -> bool:
         """
         return self._comp.get_bit(self._REG_CONTROL, 1)
 
+    @property
+    def stalled(self) -> bool:
+        """MFB transmission is blocked.
+
+        This returns true if there are valid data (i.e. SRC_RDY is set) but
+        receiver is not able to accept them (i.e. DST_RDY is cleared).
+        """
+        return self.generating and not self._comp.get_bit(self._REG_CONTROL, 2)
+
     def clear(self):
         """Clear packet counters."""
         self._comp.set_bit(self._REG_CONTROL, 4)