chore(build): update default AGILEX device in build system

jakubcabal · jakubcabal · commit 386232c07467 · 2025-09-29T12:13:16.000+02:00
diff --git a/build/targets/comp_quartus.tcl b/build/targets/comp_quartus.tcl
@@ -69,7 +69,7 @@ if {![info exists SYNTH_FLAGS(FPGA)]} {
     }
     set SYNTH_FLAGS(FPGA) [string map {
             "STRATIX10"     "1SD280PT2F55E1VG"
-            "AGILEX"        "AGIB027R29A1E2VR0"
+            "AGILEX"        "AGIB023R18A1E1V"
         } $SYNTH_FLAGS(DEVICE)]
 }
 

Original file line number	Diff line number	Diff line change
`@@ -69,7 +69,7 @@ if {![info exists SYNTH_FLAGS(FPGA)]} {`
`69`	`69`	`}`
`70`	`70`	`set SYNTH_FLAGS(FPGA) [string map {`
`71`	`71`	`"STRATIX10" "1SD280PT2F55E1VG"`
`72`		`- "AGILEX" "AGIB027R29A1E2VR0"`
	`72`	`+ "AGILEX" "AGIB023R18A1E1V"`
`73`	`73`	`} $SYNTH_FLAGS(DEVICE)]`
`74`	`74`	`}`
`75`	`75`