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jakubcabaljakubcabal
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Merge branch 'isa_cmac_uvm_fix' into 'devel'
fix(cmac-uvm): fix byte ordering See merge request ndk/ndk-fpga!294
2 parents d8a135e + 2b07244 commit 2c011af

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2 files changed

+43
-32
lines changed
  • comp/uvm/logic_vector_array_lbus
  • core/comp/eth/network_mod/uvm/tbench/cmac

2 files changed

+43
-32
lines changed

‎comp/uvm/logic_vector_array_lbus/monitor.sv‎

Lines changed: 20 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -33,22 +33,17 @@ class monitor_logic_vector_array extends uvm_logic_vector_array::monitor #(8);
3333
ready_deassertion_counter = 0;
3434
endfunction
3535

36-
protected virtual function void save_segment_by_index(uvm_lbus::sequence_item item, int unsigned segment_index, bit full_segment = 0);
37-
logic [128-1 : 0] data = item.data[128*(segment_index+1)-1 -: 128];
38-
logic [4 -1 : 0] mty = (full_segment ? 0 : item.mty[4*(segment_index+1)-1 -: 4]);
39-
save_segment(data, mty);
40-
endfunction
41-
4236
protected virtual function void save_segment(logic [128-1 : 0] data, logic [4-1 : 0] mty = 0);
43-
int unsigned valid_byte_count = (128/8)-mty;
44-
45-
for (int unsigned i = 0; i < valid_byte_count; i++) begin
37+
for (int unsigned i = (128/8); i > mty; ) begin
38+
i--;
4639
bytes.push_back(data[8*(i+1)-1 -: 8]);
4740
end
4841
endfunction
4942

5043
protected virtual function void send_packet();
51-
uvm_logic_vector_array::sequence_item #(8) item = uvm_logic_vector_array::sequence_item #(8)::type_id::create("item");
44+
uvm_logic_vector_array::sequence_item #(8) item;
45+
46+
item = uvm_logic_vector_array::sequence_item #(8)::type_id::create("item");
5247
item.data = bytes;
5348
bytes.delete();
5449
analysis_port.write(item);
@@ -80,32 +75,38 @@ class monitor_logic_vector_array extends uvm_logic_vector_array::monitor #(8);
8075

8176
if (!inside_frame) begin
8277
if (t.sop[i] === 1'b1 && t.eop[i] === 1'b1) begin
83-
save_segment_by_index(t, i);
78+
save_segment(t.data[128*(i+1)-1 -: 128], t.mty[4*(i+1)-1 -: 4]);
8479
end
8580
else if (t.sop[i] === 1'b1) begin
8681
inside_frame = 1;
87-
save_segment_by_index(t, i, 1);
82+
save_segment(t.data[128*(i+1)-1 -: 128], 0);
8883
end
8984
else begin
9085
assert(t.eop[i] !== 1'b1)
9186
else begin
92-
`uvm_error(this.get_full_name(), "\n\tThe EOP was set before a new packet transfer started. A SOP wasn't set before this EOP")
87+
string msg;
88+
// verilog_lint: waive line-length
89+
msg = "\n\tThe EOP was set before a new packet transfer started. A SOP wasn't set before this EOP";
90+
`uvm_error(this.get_full_name(), msg);
9391
end
9492
end
9593
end
9694
else begin
9795
if (t.eop[i] === 1'b1) begin
9896
inside_frame = 0;
99-
save_segment_by_index(t, i);
97+
save_segment(t.data[128*(i+1)-1 -: 128], t.mty[4*(i+1)-1 -: 4]);
10098
send_packet();
10199
end
102100
else begin
103-
save_segment_by_index(t, i, 1);
101+
save_segment(t.data[128*(i+1)-1 -: 128], 0);
104102
end
105103

106104
assert(t.sop[i] !== 1'b1)
107105
else begin
108-
`uvm_error(this.get_full_name(), "\n\tThe SOP was before the last packet transfer correctly ended. A EOP wasn't set at the end of the packet transfer")
106+
string msg;
107+
// verilog_lint: waive line-length
108+
msg = "\n\tThe SOP was before the last packet transfer correctly ended. A EOP wasn't set at the end of the packet transfer";
109+
`uvm_error(this.get_full_name(), msg);
109110
end
110111
end
111112
end
@@ -157,7 +158,9 @@ class monitor_logic_vector extends uvm_logic_vector::monitor #(1);
157158

158159
for (int unsigned i = 0; i < 4; i++) begin
159160
if (t.ena[i] === 1'b1 && t.eop[i] === 1'b1) begin
160-
uvm_logic_vector::sequence_item #(1) item = uvm_logic_vector::sequence_item #(1)::type_id::create("item");
161+
uvm_logic_vector::sequence_item #(1) item;
162+
163+
item = uvm_logic_vector::sequence_item #(1)::type_id::create("item");
161164
item.data = t.err[i];
162165
analysis_port.write(item);
163166
end

‎core/comp/eth/network_mod/uvm/tbench/cmac/dut.sv‎

Lines changed: 23 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,7 @@
44

55
// SPDX-License-Identifier: BSD-3-Clause
66

7+
// verilog_lint: waive module-filename
78
module DUT #(
89
string ETH_CORE_ARCH,
910
int unsigned ETH_PORTS,
@@ -124,22 +125,25 @@ module DUT #(
124125
);
125126

126127
generate;
127-
for (genvar eth_it = 0; eth_it < ETH_PORTS; eth_it++) begin
128-
localparam int unsigned ETH_PORT_CHAN_LOCAL = ETH_PORT_CHAN[eth_it];
129-
initial assert(ETH_PORT_CHAN_LOCAL == 1);
128+
for (genvar eth_it = 0; eth_it < ETH_PORTS; eth_it++) begin : eth_inf
129+
initial begin
130+
assert(ETH_PORT_CHAN[eth_it] == 1);
131+
end
130132

131-
wire logic [4*128-1 : 0] eth_rx_data;
132133
logic CLK_ETH_GEN = 1'b0;
133134

135+
// verilog_lint: waive explicit-begin
134136
always #(CLK_ETH_PERIOD[eth_it]/2) CLK_ETH_GEN = ~CLK_ETH_GEN;
135137

136138
// ------- //
137139
// TX side //
138140
// ------- //
139141

140-
for (genvar slice = 0; slice < 4; slice++) begin
142+
for (genvar slice = 0; slice < 4; slice++) begin : slice_tx
141143
initial begin
142-
force DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.cmac_rx_lbus_data[slice] = {<<8{eth_tx[eth_it].DATA[128*(slice+1)-1 -: 128]}}; // Byte reordering
144+
// verilog_lint: waive line-length
145+
force DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.cmac_rx_lbus_data[slice] = eth_tx[eth_it].DATA[128*(slice+1)-1 -: 128]; // Byte reordering
146+
// verilog_lint: waive line-length
143147
force DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.cmac_rx_lbus_mty [slice] = eth_tx[eth_it].MTY[4*(slice+1)-1 -: 4];
144148
end
145149
end
@@ -157,28 +161,32 @@ module DUT #(
157161
// RX side //
158162
// ------- //
159163

160-
assign eth_rx_data = {>>{DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.cmac_tx_lbus_data}};
161-
for (genvar segment = 0; segment < 4; segment++) begin
162-
wire logic [128-1 : 0] segment_data;
163-
164-
assign segment_data = eth_rx_data[128*(segment+1)-1 -: 128];
165-
assign eth_rx[eth_it].DATA[128*(segment+1)-1 -: 128] = {<<8{segment_data}}; // Byte reordering
164+
for (genvar segment = 0; segment < 4; segment++) begin : slice_rx
165+
// verilog_lint: waive line-length
166+
assign eth_rx[eth_it].DATA[128*(segment+1)-1 -: 128] = DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.cmac_tx_lbus_data[segment]; // Byte reordering
167+
// verilog_lint: waive line-length
168+
assign eth_rx[eth_it].MTY[4*(segment+1)-1 -: 4] = DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.cmac_tx_lbus_mty[segment];
166169
end
167170

168171
assign eth_rx[eth_it].ENA = DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.cmac_tx_lbus_ena;
169172
assign eth_rx[eth_it].SOP = DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.cmac_tx_lbus_sop;
170173
assign eth_rx[eth_it].EOP = DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.cmac_tx_lbus_eop;
171174
assign eth_rx[eth_it].ERR = DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.cmac_tx_lbus_err;
172-
assign eth_rx[eth_it].MTY = {>>{DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.cmac_tx_lbus_mty}};
173175

174-
initial force DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.cmac_tx_lbus_rdy = eth_rx[eth_it].RDY;
176+
// verilog_lint: waive line-length
177+
initial begin
178+
force DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.cmac_tx_lbus_rdy = eth_rx[eth_it].RDY;
179+
end
175180

176181
// ----- //
177182
// Other //
178183
// ----- //
179184

180185
// CLK connection
181-
initial force DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.cmac_gt_tx_clk_322m = CLK_ETH_GEN;
186+
// verilog_lint: waive line-length
187+
initial begin
188+
force DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.cmac_gt_tx_clk_322m = CLK_ETH_GEN;
189+
end
182190
end
183191
endgenerate
184192

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