Merge pull request #1382 from NickeZ/upgrade-asf4

external/asf4: Upgrade to latest version

Author: NickeZ

.clang-tidy

@@ -16,7 +16,8 @@ Checks: >-
   -performance-no-int-to-ptr,
   -clang-analyzer-security.insecureAPI.DeprecatedOrUnsafeBufferHandling,
   -readability-avoid-unconditional-preprocessor-if,
-  -readability-suspicious-call-argument
+  -readability-suspicious-call-argument,
+  -clang-diagnostic-incompatible-pointer-types-discards-qualifiers
 HeaderFilterRegex: '.*'
 ExtraArgs:
   - -Wno-unknown-warning-option

external/CMakeLists.txt

@@ -113,8 +113,6 @@ if(CMAKE_CROSSCOMPILING)
     asf4-drivers/hal/src/hal_io.c
     asf4-drivers/hal/src/hal_sha_sync.c
     asf4-drivers/hpl/systick/hpl_systick.c
-    asf4-drivers/hal/src/hal_usart_async.c
-    asf4-drivers/hal/utils/src/utils_ringbuffer.c
     asf4-drivers/hpl/gclk/hpl_gclk.c
     asf4-drivers/hpl/oscctrl/hpl_oscctrl.c
     asf4-drivers/hpl/mclk/hpl_mclk.c
@@ -133,6 +131,8 @@ if(CMAKE_CROSSCOMPILING)
     asf4-drivers/usb/device/usbdc.c
     )
 
+    target_compile_options(asf4-drivers-min PRIVATE -Wno-cast-qual -Wno-unused-parameter -Wno-missing-prototypes -Wno-missing-declarations -Wno-bad-function-cast -Wno-strict-prototypes -Wno-old-style-definition)
+
   target_link_libraries(asf4-drivers-min samd51a-ds)
   set_property(TARGET asf4-drivers-min PROPERTY INTERFACE_LINK_LIBRARIES "")
 
@@ -170,6 +170,9 @@ if(CMAKE_CROSSCOMPILING)
     asf4-drivers/sd_mmc/sd_mmc.c
     asf4-drivers/diskio/sdmmc_diskio.c
   )
+
+  target_compile_options(asf4-drivers PRIVATE -Wno-cast-qual -Wno-unused-parameter -Wno-switch-default -Wno-bad-function-cast -Wno-implicit-fallthrough)
+
   target_link_libraries(asf4-drivers
     PRIVATE
       samd51a-ds

external/asf4-drivers/Config/RTE_Components.h

@@ -0,0 +1,54 @@
+/* Auto-generated config file hpl_cmcc_config.h */
+#ifndef HPL_CMCC_CONFIG_H
+#define HPL_CMCC_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <h> Basic Configuration
+
+// <q> Cache enable
+//<i> Defines the cache should be enabled or not.
+// <id> cmcc_enable
+#ifndef CONF_CMCC_ENABLE
+#define CONF_CMCC_ENABLE 0x0
+#endif
+
+// <o> Cache Size
+//<i> Defines the cache memory size to be configured.
+// <0x0=>1 KB
+// <0x1=>2 KB
+// <0x2=>4 KB
+// <id> cache_size
+#ifndef CONF_CMCC_CACHE_SIZE
+#define CONF_CMCC_CACHE_SIZE 0x2
+#endif
+
+// <e> Advanced Configuration
+// <id> cmcc_advanced_configuration
+// <q> Data cache disable
+//<i> Defines the data cache should be disabled or not.
+// <id> cmcc_data_cache_disable
+#ifndef CONF_CMCC_DATA_CACHE_DISABLE
+#define CONF_CMCC_DATA_CACHE_DISABLE 0x0
+#endif
+
+// <q> Instruction cache disable
+//<i> Defines the Instruction cache should be disabled or not.
+// <id> cmcc_inst_cache_disable
+#ifndef CONF_CMCC_INST_CACHE_DISABLE
+#define CONF_CMCC_INST_CACHE_DISABLE 0x0
+#endif
+
+// <q> Clock Gating disable
+//<i> Defines the clock gating should be disabled or not.
+// <id> cmcc_clock_gating_disable
+#ifndef CONF_CMCC_CLK_GATING_DISABLE
+#define CONF_CMCC_CLK_GATING_DISABLE 0x0
+#endif
+
+// </e>
+// </h>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_CMCC_CONFIG_H

external/asf4-drivers/Config/hpl_aes_config.h

@@ -303,7 +303,7 @@
 // <i> Indicates whether Quick Lock Disable is enabled or not
 // <id> dfll_arch_qldis
 #ifndef CONF_DFLL_QLDIS
-#define CONF_DFLL_QLDIS 1//0 // FIXME - was 0; datasheet says 'should' be set for USB crystal less mode
+#define CONF_DFLL_QLDIS 1
 #endif
 
 // <q> Chill Cycle Disable
@@ -332,7 +332,7 @@
 // <1=>Closed Loop Mode
 // <id> dfll_mode
 #ifndef CONF_DFLL_MODE
-#define CONF_DFLL_MODE 0x1// FIXME - was 0x0; datasheet says should be 1 for USB crystal less mode
+#define CONF_DFLL_MODE 0x1
 #endif
 
 // <o> Coarse Maximum Step <0x0-0x1F>
@@ -344,7 +344,7 @@
 // <o> Fine Maximum Step <0x0-0xFF>
 // <id> dfll_arch_fstep
 #ifndef CONF_DFLL_FSTEP
-#define CONF_DFLL_FSTEP 0xA//0x1// FIXME - datasheet 54.14 says should be 0xA
+#define CONF_DFLL_FSTEP 0xa
 #endif
 
 // <o> DFLL Multiply Factor <0x0-0xFFFF>
@@ -430,18 +430,21 @@
 #endif
 
 // <o> Loop Divider Ratio Fractional Part <0x0-0x1F>
+// <i> Value of LDRFRAC is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
 // <id> fdpll0_ldrfrac
 #ifndef CONF_FDPLL0_LDRFRAC
 #define CONF_FDPLL0_LDRFRAC 0x0
 #endif
 
 // <o> Loop Divider Ratio Integer Part <0x0-0x1FFF>
+// <i> Value of LDR is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
 // <id> fdpll0_ldr
 #ifndef CONF_FDPLL0_LDR
 #define CONF_FDPLL0_LDR 0x2f
 #endif
 
 // <o> Clock Divider <0x0-0x7FF>
+// <i> This Clock divider is only for XOSC clock input to DPLL
 // <id> fdpll0_clock_div
 #ifndef CONF_FDPLL0_DIV
 #define CONF_FDPLL0_DIV 0x0
@@ -555,18 +558,21 @@
 #endif
 
 // <o> Loop Divider Ratio Fractional Part <0x0-0x1F>
+// <i> Value of LDRFRAC is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
 // <id> fdpll1_ldrfrac
 #ifndef CONF_FDPLL1_LDRFRAC
 #define CONF_FDPLL1_LDRFRAC 0x0
 #endif
 
 // <o> Loop Divider Ratio Integer Part <0x0-0x1FFF>
+// <i> Value of LDR is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
 // <id> fdpll1_ldr
 #ifndef CONF_FDPLL1_LDR
 #define CONF_FDPLL1_LDR 0x3b
 #endif
 
 // <o> Clock Divider <0x0-0x7FF>
+// <i> This Clock divider is only for XOSC clock input to DPLL
 // <id> fdpll1_clock_div
 #ifndef CONF_FDPLL1_DIV
 #define CONF_FDPLL1_DIV 0x0