relaxes x86 operands deconstructor to address llvm changes

Occasionally, llvm refines their instruction definitions and change
the number of operands, for example this [commit][1] added an extra
destination register operand. For the old lifters we used a pretty
strict rules for operands deconstructing and for the bts, btc, and btr
instructions we were expecting two operands (now there are three of
them).

I decided to relax the deconstructor instead of changing the
definition of instructions, first to preserve backward compatibility
with the older versions of llvm and second because many other
instructions could be affected by the same changes from the llvm side,
and I don't see any harm if we will accept instructions with one more
argument, knowing that destinations are always prepended.

[1]: llvm/llvm-project@fe96ff7

Author: ivg

plugins/x86/x86_operands.ml

@@ -28,12 +28,16 @@ let m ~f mem insn =
 
 let rr ~f mem insn =
   match Insn.ops insn with
-  | [| Op.Reg reg1; Op.Reg reg2 |] -> f mem reg1 reg2
+  | [| _; Op.Reg reg1; Op.Reg reg2 |]
+  | [| Op.Reg reg1; Op.Reg reg2 |] ->
+    f mem reg1 reg2
   | _ -> invalid_operands ~here:[%here] insn
 
 let ri ~f mem insn =
   match Insn.ops insn with
-  | [| Op.Reg reg; Op.Imm imm |] -> f mem reg imm
+  | [| _; Op.Reg reg; Op.Imm imm |]
+  | [| Op.Reg reg; Op.Imm imm |] ->
+    f mem reg imm
   | _ -> invalid_operands ~here:[%here] insn
 
 let ir ~f mem insn =