ext2: rename

Signed-off-by: Andy-Python-Programmer <andypythonappdeveloper@gmail.com>

Author: Andy-Python-Programmer

src/aero_kernel/src/drivers/block/ide/mod.rs

@@ -79,6 +79,15 @@ impl BlockDeviceInterface for IdeDrive {
         unimplemented!()
     }
 
+    fn write_dma(
+        &self,
+        _sector: usize,
+        _start: crate::mem::paging::PhysAddr,
+        _size: usize,
+    ) -> Option<usize> {
+        todo!()
+    }
+
     fn write_block(&self, _sector: usize, _buf: &[u8]) -> Option<usize> {
         unimplemented!()
     }

src/aero_kernel/src/drivers/block/nvme/command.rs

@@ -39,6 +39,7 @@ bitflags::bitflags! {
 #[repr(u8)]
 #[derive(Default, Copy, Clone)]
 pub enum CommandOpcode {
+    Write = 0x1,
     Read = 0x2,
 
     #[default]

src/aero_kernel/src/drivers/block/nvme/mod.rs

@@ -230,13 +230,13 @@ struct Namespace<'a> {
 }
 
 impl<'a> Namespace<'a> {
-    fn read(&self, sector: usize, start: PhysAddr, size_bytes: usize) {
+    fn rw_command(&self, opcode: CommandOpcode, sector: usize, start: PhysAddr, size_bytes: usize) {
         assert!(size_bytes != 0);
 
         let blocks = size_bytes.ceil_div(self.block_size);
         let mut read_cmd = ReadWriteCommand::default();
 
-        read_cmd.opcode = CommandOpcode::Read as u8;
+        read_cmd.opcode = opcode as u8;
         read_cmd.nsid = self.nsid;
         read_cmd.start_lba = sector as u64;
         read_cmd.length = (blocks - 1) as u16;
@@ -463,13 +463,23 @@ impl<'a> Controller<'a> {
 
 impl<'a> BlockDeviceInterface for Controller<'a> {
     fn read_dma(&self, sector: usize, start: PhysAddr, size: usize) -> Option<usize> {
-        self.namespaces.lock()[0].read(sector, start, size);
+        self.namespaces.lock()[0].rw_command(CommandOpcode::Read, sector, start, size);
+        Some(size)
+    }
+
+    fn write_dma(&self, sector: usize, start: PhysAddr, size: usize) -> Option<usize> {
+        self.namespaces.lock()[0].rw_command(CommandOpcode::Write, sector, start, size);
         Some(size)
     }
 
     fn read_block(&self, sector: usize, dest: &mut [MaybeUninit<u8>]) -> Option<usize> {
         let buffer = Dma::<u8>::new_uninit_slice(dest.len());
-        self.namespaces.lock()[0].read(sector, buffer.addr(), dest.len());
+        self.namespaces.lock()[0].rw_command(
+            CommandOpcode::Read,
+            sector,
+            buffer.addr(),
+            dest.len(),
+        );
 
         // SAFETY: The buffer is initialized above.
         dest.copy_from_slice(&buffer);

src/aero_kernel/src/fs/block/mod.rs

@@ -22,6 +22,8 @@ mod gpt;
 use gpt::Gpt;
 
 use core::mem::MaybeUninit;
+use core::ops::{Deref, DerefMut};
+use core::sync::atomic::{AtomicBool, Ordering};
 
 use alloc::collections::BTreeMap;
 use alloc::sync::{Arc, Weak};
@@ -45,6 +47,7 @@ struct CachedPage {
     device: Weak<dyn CachedAccess>,
     offset: usize,
     page: PhysFrame,
+    dirty: AtomicBool,
 }
 
 impl CachedPage {
@@ -55,6 +58,7 @@ impl CachedPage {
             page: FRAME_ALLOCATOR
                 .allocate_frame()
                 .expect("page_cache: out of memory"),
+            dirty: AtomicBool::new(false),
         }
     }
 
@@ -77,6 +81,39 @@ impl CachedPage {
     fn make_key(device: Weak<dyn CachedAccess>, offset: usize) -> PageCacheKey {
         (device.as_ptr() as *const u8 as usize, offset)
     }
+
+    /// Returns whether the page has been marked dirty.
+    fn is_dirty(&self) -> bool {
+        self.dirty.load(Ordering::SeqCst)
+    }
+
+    fn mark_dirty(&self) {
+        self.dirty.store(true, Ordering::SeqCst);
+    }
+
+    fn device(&self) -> Arc<dyn CachedAccess> {
+        self.device.upgrade().unwrap()
+    }
+
+    fn sync(&self) {
+        if !self.is_dirty() {
+            return;
+        }
+
+        // Commit the changes made to the cache to the disk.
+        let disk = self.device();
+
+        let offset_bytes = self.offset * Size4KiB::SIZE as usize;
+        let sector = offset_bytes / disk.block_size();
+
+        disk.write_dma(sector, self.data_addr(), Size4KiB::SIZE as usize);
+    }
+}
+
+impl Drop for CachedPage {
+    fn drop(&mut self) {
+        self.sync()
+    }
 }
 
 impl Cacheable<PageCacheKey> for CachedPage {
@@ -96,9 +133,8 @@ impl Cache<PageCacheKey, CachedPage> {
     /// ## Arguments
     ///
     /// * `device` - The device to get the page from.
-    ///
-    /// * `offset` - The offset in bytes to the data. This will be rounded down to
-    ///              the nearest page boundary.
+    /// * `offset` - The offset in bytes to the data. This will be rounded down to the nearest page
+    ///   boundary.
     pub fn get_page(&self, device: Weak<dyn CachedAccess>, offset: usize) -> PageCacheItem {
         let cache_offset = offset / Size4KiB::SIZE as usize;
         let cache_key = CachedPage::make_key(device.clone(), cache_offset);
@@ -121,10 +157,48 @@ impl Cache<PageCacheKey, CachedPage> {
     }
 }
 
+pub struct DirtyRef<T: Sized> {
+    cache: PageCacheItem,
+    ptr: *mut T,
+}
+
+impl<T> DirtyRef<T> {
+    pub fn new(device: Weak<dyn CachedAccess>, offset: usize) -> Self {
+        let cache = PAGE_CACHE.get_page(device, offset);
+
+        let ptr_offset = offset % Size4KiB::SIZE as usize;
+        let ptr = &cache.data_mut()[ptr_offset..ptr_offset + core::mem::size_of::<T>()];
+
+        Self {
+            ptr: ptr.as_ptr() as *mut T,
+            cache,
+        }
+    }
+}
+
+impl<T> Deref for DirtyRef<T> {
+    type Target = T;
+
+    fn deref(&self) -> &Self::Target {
+        unsafe { &*self.ptr }
+    }
+}
+
+impl<T> DerefMut for DirtyRef<T> {
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        self.cache.mark_dirty();
+        unsafe { &mut *self.ptr }
+    }
+}
+
+unsafe impl<T> Sync for DirtyRef<T> {}
+unsafe impl<T> Send for DirtyRef<T> {}
+
 pub trait BlockDeviceInterface: Send + Sync {
     fn block_size(&self) -> usize;
 
     fn read_dma(&self, sector: usize, start: PhysAddr, size: usize) -> Option<usize>;
+    fn write_dma(&self, sector: usize, start: PhysAddr, size: usize) -> Option<usize>;
 
     fn read_block(&self, sector: usize, dest: &mut [MaybeUninit<u8>]) -> Option<usize>;
     fn write_block(&self, sector: usize, buf: &[u8]) -> Option<usize>;
@@ -228,6 +302,10 @@ impl BlockDeviceInterface for BlockDevice {
         self.dev.read_dma(sector, start, size)
     }
 
+    fn write_dma(&self, sector: usize, start: PhysAddr, size: usize) -> Option<usize> {
+        self.dev.write_dma(sector, start, size)
+    }
+
     fn read_block(&self, sector: usize, dest: &mut [MaybeUninit<u8>]) -> Option<usize> {
         self.dev.read_block(sector, dest)
     }
@@ -292,6 +370,14 @@ impl BlockDeviceInterface for PartitionBlockDevice {
         self.device.write_block(self.offset + sector, buf)
     }
 
+    fn write_dma(&self, sector: usize, start: PhysAddr, size: usize) -> Option<usize> {
+        if sector >= self.size {
+            return None;
+        }
+
+        self.write_dma(self.offset + sector, start, size)
+    }
+
     fn read_dma(&self, sector: usize, start: PhysAddr, size: usize) -> Option<usize> {
         if sector >= self.size {
             return None;

src/aero_kernel/src/fs/cache.rs

@@ -249,6 +249,20 @@ impl<K: CacheKey, V: Cacheable<K>> Cache<K, V> {
         }
     }
 
+    pub fn rehash<F>(&self, item: CacheArc<CacheItem<K, V>>, update: F)
+    where
+        F: FnOnce(),
+    {
+        let mut index = self.index.lock();
+        let key = item.cache_key();
+
+        index.used.remove(&key).expect("cache: item is not used");
+        update();
+
+        let new_key = item.cache_key();
+        index.used.insert(new_key, Arc::downgrade(&item));
+    }
+
     pub fn log(&self) {
         let index = self.index.lock();
 

src/aero_kernel/src/fs/ext2/disk.rs

@@ -166,12 +166,6 @@ impl DirEntry {
 
         name_bytes.copy_from_slice(name.as_bytes());
     }
-
-    pub fn as_bytes(&self) -> &[u8] {
-        unsafe {
-            core::slice::from_raw_parts(self as *const Self as *const u8, self.entry_size as usize)
-        }
-    }
 }
 
 #[repr(u8)]