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CPU build updated; constructors updated due to Config Builder usage
1 parent 1e9f94d commit 45b92e1

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3 files changed

+26
-8
lines changed

3 files changed

+26
-8
lines changed

CacheSimulator/CPU.cs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -7,14 +7,14 @@ public class CPU
77
{
88
private List<CpuCore> cores { get; set; }
99

10-
public CPU((string ramFileName, int size, int associativity, int blockSize, WritePolicy writeHitPolicy, WritePolicy writeMissPolicy, ReplacementPolicy replacementPolicy) cacheInfo, int numberOfCores)
10+
public CPU((string ramFileName, int size, int associativity) cacheInfo, CacheConfiguration config, int numberOfCores)
1111
{
1212
cores = new List<CpuCore>(numberOfCores);
1313

1414
//CPU cores initialization.
1515
for (var i = 0; i < numberOfCores; ++i)
1616
{
17-
cores.Add(new CpuCore(cacheInfo));
17+
cores.Add(new CpuCore(cacheInfo, config));
1818
}
1919
}
2020

CacheSimulator/CpuCore.cs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -9,9 +9,9 @@ public class CpuCore
99
{
1010
private Cache L1d;
1111

12-
public CpuCore((string ramFileName, int size, int associativity, int blockSize, WritePolicy writeHitPolicy, WritePolicy writeMissPolicy, ReplacementPolicy replacementPolicy) cacheInfo)
12+
public CpuCore((string ramFileName, int size, int associativity) cacheInfo, CacheConfiguration config)
1313
{
14-
L1d = new Cache(cacheInfo);
14+
L1d = new Cache(cacheInfo, config);
1515
}
1616

1717
public string ExecuteTraceLine(string traceLine, int traceIndex, int coreNumber)

CacheSimulator/MainWindow.xaml.cs

Lines changed: 22 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -76,18 +76,19 @@ private async void StartSimulation(object sender, RoutedEventArgs e)
7676
try
7777
{
7878
var size = Int32.Parse(cacheSize.Text);
79-
var lineSize = Int32.Parse(cacheLineSize.Text);
8079

81-
var associativity = GetCacheAssociativity(size, lineSize);
80+
var associativity = GetCacheAssociativity(size, GetCacheLineSize());
8281
var numberOfCores = GetNumberOfCores();
8382

8483
if (numberOfCores > 128)
8584
{
8685
numberOfCores = 128;
8786
}
8887

89-
cpu = new CPU((ramFileFullPath, size, associativity, lineSize,
90-
GetWritePolicy(cacheWriteHitPolicyComboBox.Text), GetWritePolicy(cacheWriteMissPolicyComboBox.Text), GetReplacementPolicy(cacheReplacementPolicyComboBox.Text)), numberOfCores);
88+
// Build cache config information.
89+
var cacheConfigBuilder = GetCacheConfigBuilder();
90+
91+
cpu = new CPU((ramFileFullPath, size, associativity), cacheConfigBuilder.Build(), numberOfCores);
9192

9293
logLines.Append($"Simulation {numberOfSimulation++}\n");
9394

@@ -207,6 +208,18 @@ private async void StartSimulation(object sender, RoutedEventArgs e)
207208
EnableWindowComponents(true);
208209
}
209210

211+
212+
private CacheConfigurationBuilder GetCacheConfigBuilder()
213+
{
214+
var cacheConfigBuilder = new CacheConfigurationBuilder();
215+
cacheConfigBuilder.Size(GetCacheLineSize());
216+
cacheConfigBuilder.WriteHitPolicy(GetWritePolicy(cacheWriteHitPolicyComboBox.Text));
217+
cacheConfigBuilder.WriteMissPolicy(GetWritePolicy(cacheWriteMissPolicyComboBox.Text));
218+
cacheConfigBuilder.ReplacementPolicy(GetReplacementPolicy(cacheReplacementPolicyComboBox.Text));
219+
220+
return cacheConfigBuilder;
221+
}
222+
210223
private void StopSimulation(object sender, RoutedEventArgs e)
211224
{
212225
if (!isRunning || isCancelRequested)
@@ -218,6 +231,11 @@ private void StopSimulation(object sender, RoutedEventArgs e)
218231
source.Cancel();
219232
}
220233

234+
private int GetCacheLineSize()
235+
{
236+
return Int32.Parse(cacheLineSize.Text);
237+
}
238+
221239
private int GetCacheAssociativity(int cacheSize, int lineSize)
222240
{
223241
return cacheAssociativityComboBox.Text switch

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