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Update cmsis files
Signed-off-by: Sadik.Ozer <Sadik.Ozer@maximintegrated.com>
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‎targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/aes_key_regs.h‎

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/**
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* @file aes_key_regs.h
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* @brief Registers, Bit Masks and Bit Positions for the AES_KEY Peripheral Module.
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*/
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/* ****************************************************************************
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* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
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* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Except as contained in this notice, the name of Maxim Integrated
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* Products, Inc. shall not be used except as stated in the Maxim Integrated
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* Products, Inc. Branding Policy.
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*
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* The mere transfer of this software does not imply any licenses
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* of trade secrets, proprietary technology, copyrights, patents,
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* trademarks, maskwork rights, or any other form of intellectual
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* property whatsoever. Maxim Integrated Products, Inc. retains all
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* ownership rights.
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*
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*
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*************************************************************************** */
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#ifndef _AES_KEY_REGS_H_
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#define _AES_KEY_REGS_H_
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/* **** Includes **** */
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if defined (__ICCARM__)
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#pragma system_include
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#endif
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#if defined (__CC_ARM)
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#pragma anon_unions
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#endif
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/// @cond
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/*
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If types are not defined elsewhere (CMSIS) define them here
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*/
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#ifndef __IO
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#define __IO volatile
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#endif
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#ifndef __I
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#define __I volatile const
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#endif
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#ifndef __O
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#define __O volatile
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#endif
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#ifndef __R
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#define __R volatile const
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#endif
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/// @endcond
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/* **** Definitions **** */
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/**
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* @ingroup aes_key
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* @defgroup aes_key_registers AES_KEY_Registers
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* @brief Registers, Bit Masks and Bit Positions for the AES_KEY Peripheral Module.
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* @details AES Key Registers.
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*/
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/**
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* @ingroup aes_key_registers
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* Structure type to access the AES_KEY Registers.
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*/
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typedef struct {
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__IO uint32_t aes_key0; /**< <tt>\b 0x00:</tt> AES_KEY AES_KEY0 Register */
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__IO uint32_t aes_key1; /**< <tt>\b 0x04:</tt> AES_KEY AES_KEY1 Register */
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__IO uint32_t aes_key2; /**< <tt>\b 0x08:</tt> AES_KEY AES_KEY2 Register */
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__IO uint32_t aes_key3; /**< <tt>\b 0x0C:</tt> AES_KEY AES_KEY3 Register */
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__IO uint32_t aes_key4; /**< <tt>\b 0x10:</tt> AES_KEY AES_KEY4 Register */
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__IO uint32_t aes_key5; /**< <tt>\b 0x14:</tt> AES_KEY AES_KEY5 Register */
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__IO uint32_t aes_key6; /**< <tt>\b 0x18:</tt> AES_KEY AES_KEY6 Register */
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__IO uint32_t aes_key7; /**< <tt>\b 0x1C:</tt> AES_KEY AES_KEY7 Register */
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} mxc_aes_key_regs_t;
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/* Register offsets for module AES_KEY */
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/**
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* @ingroup aes_key_registers
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* @defgroup AES_KEY_Register_Offsets Register Offsets
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* @brief AES_KEY Peripheral Register Offsets from the AES_KEY Base Peripheral Address.
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* @{
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*/
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#define MXC_R_AES_KEY_AES_KEY0 ((uint32_t)0x00000000UL) /**< Offset from AES_KEY Base Address: <tt> 0x0000</tt> */
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#define MXC_R_AES_KEY_AES_KEY1 ((uint32_t)0x00000004UL) /**< Offset from AES_KEY Base Address: <tt> 0x0004</tt> */
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#define MXC_R_AES_KEY_AES_KEY2 ((uint32_t)0x00000008UL) /**< Offset from AES_KEY Base Address: <tt> 0x0008</tt> */
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#define MXC_R_AES_KEY_AES_KEY3 ((uint32_t)0x0000000CUL) /**< Offset from AES_KEY Base Address: <tt> 0x000C</tt> */
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#define MXC_R_AES_KEY_AES_KEY4 ((uint32_t)0x00000010UL) /**< Offset from AES_KEY Base Address: <tt> 0x0010</tt> */
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#define MXC_R_AES_KEY_AES_KEY5 ((uint32_t)0x00000014UL) /**< Offset from AES_KEY Base Address: <tt> 0x0014</tt> */
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#define MXC_R_AES_KEY_AES_KEY6 ((uint32_t)0x00000018UL) /**< Offset from AES_KEY Base Address: <tt> 0x0018</tt> */
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#define MXC_R_AES_KEY_AES_KEY7 ((uint32_t)0x0000001CUL) /**< Offset from AES_KEY Base Address: <tt> 0x001C</tt> */
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/**@} end of group aes_key_registers */
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#ifdef __cplusplus
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}
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#endif
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#endif /* _AES_KEY_REGS_H_ */

‎targets/TARGET_Maxim/TARGET_MAX32670/Libraries/CMSIS/Device/Maxim/MAX32670/Include/aes_regs.h‎

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/**
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* @file aes_regs.h
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* @brief Registers, Bit Masks and Bit Positions for the AES Peripheral Module.
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*/
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/* ****************************************************************************
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* Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
13+
* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
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* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Except as contained in this notice, the name of Maxim Integrated
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* Products, Inc. shall not be used except as stated in the Maxim Integrated
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* Products, Inc. Branding Policy.
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*
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* The mere transfer of this software does not imply any licenses
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* of trade secrets, proprietary technology, copyrights, patents,
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* trademarks, maskwork rights, or any other form of intellectual
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* property whatsoever. Maxim Integrated Products, Inc. retains all
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* ownership rights.
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*
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*
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*************************************************************************** */
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#ifndef _AES_REGS_H_
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#define _AES_REGS_H_
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/* **** Includes **** */
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if defined (__ICCARM__)
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#pragma system_include
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#endif
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#if defined (__CC_ARM)
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#pragma anon_unions
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#endif
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/// @cond
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/*
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If types are not defined elsewhere (CMSIS) define them here
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*/
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#ifndef __IO
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#define __IO volatile
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#endif
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#ifndef __I
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#define __I volatile const
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#endif
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#ifndef __O
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#define __O volatile
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#endif
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#ifndef __R
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#define __R volatile const
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#endif
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/// @endcond
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/* **** Definitions **** */
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/**
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* @ingroup aes
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* @defgroup aes_registers AES_Registers
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* @brief Registers, Bit Masks and Bit Positions for the AES Peripheral Module.
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* @details AES Keys.
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*/
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/**
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* @ingroup aes_registers
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* Structure type to access the AES Registers.
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*/
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typedef struct {
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__IO uint32_t ctrl; /**< <tt>\b 0x0000:</tt> AES CTRL Register */
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__IO uint32_t status; /**< <tt>\b 0x0004:</tt> AES STATUS Register */
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__IO uint32_t intfl; /**< <tt>\b 0x0008:</tt> AES INTFL Register */
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__IO uint32_t inten; /**< <tt>\b 0x000C:</tt> AES INTEN Register */
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__IO uint32_t fifo; /**< <tt>\b 0x0010:</tt> AES FIFO Register */
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} mxc_aes_regs_t;
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/* Register offsets for module AES */
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/**
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* @ingroup aes_registers
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* @defgroup AES_Register_Offsets Register Offsets
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* @brief AES Peripheral Register Offsets from the AES Base Peripheral Address.
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* @{
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*/
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#define MXC_R_AES_CTRL ((uint32_t)0x00000000UL) /**< Offset from AES Base Address: <tt> 0x0000</tt> */
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#define MXC_R_AES_STATUS ((uint32_t)0x00000004UL) /**< Offset from AES Base Address: <tt> 0x0004</tt> */
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#define MXC_R_AES_INTFL ((uint32_t)0x00000008UL) /**< Offset from AES Base Address: <tt> 0x0008</tt> */
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#define MXC_R_AES_INTEN ((uint32_t)0x0000000CUL) /**< Offset from AES Base Address: <tt> 0x000C</tt> */
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#define MXC_R_AES_FIFO ((uint32_t)0x00000010UL) /**< Offset from AES Base Address: <tt> 0x0010</tt> */
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/**@} end of group aes_registers */
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/**
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* @ingroup aes_registers
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* @defgroup AES_CTRL AES_CTRL
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* @brief AES Control Register
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* @{
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*/
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#define MXC_F_AES_CTRL_EN_POS 0 /**< CTRL_EN Position */
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#define MXC_F_AES_CTRL_EN ((uint32_t)(0x1UL << MXC_F_AES_CTRL_EN_POS)) /**< CTRL_EN Mask */
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#define MXC_F_AES_CTRL_DMA_RX_EN_POS 1 /**< CTRL_DMA_RX_EN Position */
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#define MXC_F_AES_CTRL_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_AES_CTRL_DMA_RX_EN_POS)) /**< CTRL_DMA_RX_EN Mask */
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#define MXC_F_AES_CTRL_DMA_TX_EN_POS 2 /**< CTRL_DMA_TX_EN Position */
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#define MXC_F_AES_CTRL_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_AES_CTRL_DMA_TX_EN_POS)) /**< CTRL_DMA_TX_EN Mask */
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#define MXC_F_AES_CTRL_START_POS 3 /**< CTRL_START Position */
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#define MXC_F_AES_CTRL_START ((uint32_t)(0x1UL << MXC_F_AES_CTRL_START_POS)) /**< CTRL_START Mask */
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#define MXC_F_AES_CTRL_INPUT_FLUSH_POS 4 /**< CTRL_INPUT_FLUSH Position */
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#define MXC_F_AES_CTRL_INPUT_FLUSH ((uint32_t)(0x1UL << MXC_F_AES_CTRL_INPUT_FLUSH_POS)) /**< CTRL_INPUT_FLUSH Mask */
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#define MXC_F_AES_CTRL_OUTPUT_FLUSH_POS 5 /**< CTRL_OUTPUT_FLUSH Position */
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#define MXC_F_AES_CTRL_OUTPUT_FLUSH ((uint32_t)(0x1UL << MXC_F_AES_CTRL_OUTPUT_FLUSH_POS)) /**< CTRL_OUTPUT_FLUSH Mask */
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#define MXC_F_AES_CTRL_KEY_SIZE_POS 6 /**< CTRL_KEY_SIZE Position */
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#define MXC_F_AES_CTRL_KEY_SIZE ((uint32_t)(0x3UL << MXC_F_AES_CTRL_KEY_SIZE_POS)) /**< CTRL_KEY_SIZE Mask */
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#define MXC_V_AES_CTRL_KEY_SIZE_AES128 ((uint32_t)0x0UL) /**< CTRL_KEY_SIZE_AES128 Value */
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#define MXC_S_AES_CTRL_KEY_SIZE_AES128 (MXC_V_AES_CTRL_KEY_SIZE_AES128 << MXC_F_AES_CTRL_KEY_SIZE_POS) /**< CTRL_KEY_SIZE_AES128 Setting */
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#define MXC_V_AES_CTRL_KEY_SIZE_AES192 ((uint32_t)0x1UL) /**< CTRL_KEY_SIZE_AES192 Value */
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#define MXC_S_AES_CTRL_KEY_SIZE_AES192 (MXC_V_AES_CTRL_KEY_SIZE_AES192 << MXC_F_AES_CTRL_KEY_SIZE_POS) /**< CTRL_KEY_SIZE_AES192 Setting */
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#define MXC_V_AES_CTRL_KEY_SIZE_AES256 ((uint32_t)0x2UL) /**< CTRL_KEY_SIZE_AES256 Value */
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#define MXC_S_AES_CTRL_KEY_SIZE_AES256 (MXC_V_AES_CTRL_KEY_SIZE_AES256 << MXC_F_AES_CTRL_KEY_SIZE_POS) /**< CTRL_KEY_SIZE_AES256 Setting */
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#define MXC_F_AES_CTRL_TYPE_POS 8 /**< CTRL_TYPE Position */
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#define MXC_F_AES_CTRL_TYPE ((uint32_t)(0x3UL << MXC_F_AES_CTRL_TYPE_POS)) /**< CTRL_TYPE Mask */
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/**@} end of group AES_CTRL_Register */
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/**
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* @ingroup aes_registers
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* @defgroup AES_STATUS AES_STATUS
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* @brief AES Status Register
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* @{
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*/
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#define MXC_F_AES_STATUS_BUSY_POS 0 /**< STATUS_BUSY Position */
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#define MXC_F_AES_STATUS_BUSY ((uint32_t)(0x1UL << MXC_F_AES_STATUS_BUSY_POS)) /**< STATUS_BUSY Mask */
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#define MXC_F_AES_STATUS_INPUT_EM_POS 1 /**< STATUS_INPUT_EM Position */
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#define MXC_F_AES_STATUS_INPUT_EM ((uint32_t)(0x1UL << MXC_F_AES_STATUS_INPUT_EM_POS)) /**< STATUS_INPUT_EM Mask */
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#define MXC_F_AES_STATUS_INPUT_FULL_POS 2 /**< STATUS_INPUT_FULL Position */
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#define MXC_F_AES_STATUS_INPUT_FULL ((uint32_t)(0x1UL << MXC_F_AES_STATUS_INPUT_FULL_POS)) /**< STATUS_INPUT_FULL Mask */
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#define MXC_F_AES_STATUS_OUTPUT_EM_POS 3 /**< STATUS_OUTPUT_EM Position */
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#define MXC_F_AES_STATUS_OUTPUT_EM ((uint32_t)(0x1UL << MXC_F_AES_STATUS_OUTPUT_EM_POS)) /**< STATUS_OUTPUT_EM Mask */
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#define MXC_F_AES_STATUS_OUTPUT_FULL_POS 4 /**< STATUS_OUTPUT_FULL Position */
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#define MXC_F_AES_STATUS_OUTPUT_FULL ((uint32_t)(0x1UL << MXC_F_AES_STATUS_OUTPUT_FULL_POS)) /**< STATUS_OUTPUT_FULL Mask */
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/**@} end of group AES_STATUS_Register */
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/**
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* @ingroup aes_registers
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* @defgroup AES_INTFL AES_INTFL
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* @brief AES Interrupt Flag Register
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* @{
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*/
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#define MXC_F_AES_INTFL_DONE_POS 0 /**< INTFL_DONE Position */
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#define MXC_F_AES_INTFL_DONE ((uint32_t)(0x1UL << MXC_F_AES_INTFL_DONE_POS)) /**< INTFL_DONE Mask */
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#define MXC_F_AES_INTFL_KEY_CHANGE_POS 1 /**< INTFL_KEY_CHANGE Position */
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#define MXC_F_AES_INTFL_KEY_CHANGE ((uint32_t)(0x1UL << MXC_F_AES_INTFL_KEY_CHANGE_POS)) /**< INTFL_KEY_CHANGE Mask */
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#define MXC_F_AES_INTFL_KEY_ZERO_POS 2 /**< INTFL_KEY_ZERO Position */
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#define MXC_F_AES_INTFL_KEY_ZERO ((uint32_t)(0x1UL << MXC_F_AES_INTFL_KEY_ZERO_POS)) /**< INTFL_KEY_ZERO Mask */
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#define MXC_F_AES_INTFL_OV_POS 3 /**< INTFL_OV Position */
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#define MXC_F_AES_INTFL_OV ((uint32_t)(0x1UL << MXC_F_AES_INTFL_OV_POS)) /**< INTFL_OV Mask */
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/**@} end of group AES_INTFL_Register */
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/**
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* @ingroup aes_registers
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* @defgroup AES_INTEN AES_INTEN
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* @brief AES Interrupt Enable Register
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* @{
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*/
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#define MXC_F_AES_INTEN_DONE_POS 0 /**< INTEN_DONE Position */
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#define MXC_F_AES_INTEN_DONE ((uint32_t)(0x1UL << MXC_F_AES_INTEN_DONE_POS)) /**< INTEN_DONE Mask */
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#define MXC_F_AES_INTEN_KEY_CHANGE_POS 1 /**< INTEN_KEY_CHANGE Position */
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#define MXC_F_AES_INTEN_KEY_CHANGE ((uint32_t)(0x1UL << MXC_F_AES_INTEN_KEY_CHANGE_POS)) /**< INTEN_KEY_CHANGE Mask */
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#define MXC_F_AES_INTEN_KEY_ZERO_POS 2 /**< INTEN_KEY_ZERO Position */
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#define MXC_F_AES_INTEN_KEY_ZERO ((uint32_t)(0x1UL << MXC_F_AES_INTEN_KEY_ZERO_POS)) /**< INTEN_KEY_ZERO Mask */
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#define MXC_F_AES_INTEN_OV_POS 3 /**< INTEN_OV Position */
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#define MXC_F_AES_INTEN_OV ((uint32_t)(0x1UL << MXC_F_AES_INTEN_OV_POS)) /**< INTEN_OV Mask */
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/**@} end of group AES_INTEN_Register */
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/**
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* @ingroup aes_registers
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* @defgroup AES_FIFO AES_FIFO
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* @brief AES Data Register
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* @{
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*/
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#define MXC_F_AES_FIFO_DATA_POS 0 /**< FIFO_DATA Position */
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#define MXC_F_AES_FIFO_DATA ((uint32_t)(0x1UL << MXC_F_AES_FIFO_DATA_POS)) /**< FIFO_DATA Mask */
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/**@} end of group AES_FIFO_Register */
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#ifdef __cplusplus
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}
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#endif
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#endif /* _AES_REGS_H_ */

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