Merge pull request #12176 from OpenNuvoton/nuvoton_usbd

Nuvoton: Support usbd

Author: 0xc0170

TESTS/usb_device/msd/main.cpp

@@ -33,8 +33,8 @@
 #include "HeapBlockDevice.h"
 #include "FATFileSystem.h"
 
-
-#if !defined(DEVICE_USBDEVICE) || !DEVICE_USBDEVICE
+// TARGET_NANO100 SRAM 16KB can't afford mass-storage-disk test, so skip usb_msd_test.
+#if !defined(DEVICE_USBDEVICE) || !DEVICE_USBDEVICE || TARGET_NANO100
 #error [NOT_SUPPORTED] USB Device not supported for this target
 #else
 

drivers/source/usb/USBCDC.cpp

@@ -464,8 +464,8 @@ void USBCDC::_receive_isr_start()
 {
     if ((_rx_size == 0) && !_rx_in_progress) {
         // Refill the buffer
-        read_start(_bulk_out, _rx_buffer, sizeof(_rx_buffer));
         _rx_in_progress = true;
+        read_start(_bulk_out, _rx_buffer, sizeof(_rx_buffer));
     }
 }
 

targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_clk.h

@@ -64,6 +64,7 @@ extern "C"
 #define CLK_CLKSEL0_SDH0SEL_HCLK        (0x02UL<<CLK_CLKSEL0_SDH0SEL_Pos) /*!< Setting SDH0 clock source as HCLK */
 #define CLK_CLKSEL0_SDH0SEL_HIRC        (0x03UL<<CLK_CLKSEL0_SDH0SEL_Pos) /*!< Setting SDH0 clock source as HIRC */
 
+#define CLK_CLKSEL0_USBSEL_HIRC48       (0x00UL<<CLK_CLKSEL0_USBSEL_Pos)  /*!< Setting USB clock source as HIRC48 */
 #define CLK_CLKSEL0_USBSEL_PLL          (0x01UL<<CLK_CLKSEL0_USBSEL_Pos)  /*!< Setting USB clock source as PLL */
 
 

targets/TARGET_NUVOTON/TARGET_NANO100/device/StdDriver/nano100_usbd.h

@@ -9,7 +9,10 @@
  ******************************************************************************/
 #ifndef __USBD_H__
 #define __USBD_H__
-
+#ifdef __cplusplus
+extern "C"
+{
+#endif
 
 /** @addtogroup NANO100_Device_Driver NANO100 Device Driver
   @{
@@ -501,6 +504,9 @@ void USBD_LockEpStall(uint32_t u32EpBitmap);
 
 /*@}*/ /* end of group NANO100_Device_Driver */
 
+#ifdef __cplusplus
+}
+#endif
 
 #endif //__USBD_H__
 

targets/TARGET_NUVOTON/TARGET_NANO100/mbed_overrides.c

@@ -64,7 +64,7 @@ void mbed_sdk_init(void)
      *    T2. <1 ms with HIRC-clocked PLL as HCLK clock source
      *    T1 will fail Greentea test which requires max 10 ms wake-up time.
      *
-     *    If we just call CLK_SetCoreClock(FREQ_42MHZ) to configure HCLK to 42 MHz,
+     *    If we just call CLK_SetCoreClock(FREQ_48MHZ) to configure HCLK to 48 MHz,
      *    it will go T1 with HXT already enabled in front. So we manually configure
      *    it to choose HXT/HIRC-clocked PLL.
      */
@@ -76,10 +76,10 @@ void mbed_sdk_init(void)
 #endif
 
 #if (NU_CLOCK_PLL == NU_HXT_PLL)
-    CLK_EnablePLL(CLK_PLLCTL_PLL_SRC_HXT, FREQ_42MHZ*2);
+    CLK_EnablePLL(CLK_PLLCTL_PLL_SRC_HXT, FREQ_48MHZ*2);
     CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL, CLK_HCLK_CLK_DIVIDER(2));
 #elif (NU_CLOCK_PLL == NU_HIRC_PLL)
-    CLK_EnablePLL(CLK_PLLCTL_PLL_SRC_HIRC, FREQ_42MHZ*2);
+    CLK_EnablePLL(CLK_PLLCTL_PLL_SRC_HIRC, FREQ_48MHZ*2);
     CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL, CLK_HCLK_CLK_DIVIDER(2));
 #endif