Update psoc6pdl to version 1.4.0

Author: dustin-crossman

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct

@@ -189,15 +189,13 @@ LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000)
     }
 
     ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0
+    ARM_LIB_HEAP  +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
     { 
-        * (HEAP) 
     }
-
+    
     ; Stack region growing down
-    ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE
+    ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE 
     {
-        * (STACK)
     }
 }
 

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S

@@ -23,36 +23,6 @@
 ; * limitations under the License.
 ; */
 
-;/*
-;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-;*/
-
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-                IF :DEF:__STACK_SIZE
-Stack_Size      EQU     __STACK_SIZE
-                ELSE
-Stack_Size      EQU     0x00000400
-                ENDIF
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-                IF :DEF:__HEAP_SIZE
-Heap_Size       EQU     __HEAP_SIZE
-                ELSE
-Heap_Size       EQU     0x00000400
-                ENDIF
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-
                 PRESERVE8
                 THUMB
 
@@ -62,8 +32,9 @@ __heap_limit
                 EXPORT  __Vectors
                 EXPORT  __Vectors_End
                 EXPORT  __Vectors_Size
+                IMPORT  |Image$$ARM_LIB_STACK$$ZI$$Limit|
 
-__Vectors       DCD     __initial_sp              ; Top of Stack
+__Vectors       DCD     |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
                 DCD     Reset_Handler             ; Reset Handler
 
                 DCD     0x0000000D                ; NMI Handler located at ROM code
@@ -284,23 +255,6 @@ NvicMux31_IRQHandler
 
                 ALIGN
 
-
-; User Initial Stack & Heap
-
-                IF      :DEF:__MICROLIB
-
-                EXPORT  __initial_sp
-                EXPORT  __heap_base
-                EXPORT  __heap_limit
-
-                ELSE
-
-                IMPORT __use_two_region_memory
-
-                ALIGN
-
-                ENDIF
-
                 END
 
 

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM0P/system_psoc6_cm0plus.c

@@ -54,8 +54,6 @@
 /** Default SlowClk system core frequency in Hz */
 #define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT       (4000000UL)
 
-/** ALTLF frequency in Hz */
-#define CY_CLK_ALTLF_FREQ_HZ                (32768UL)
 
 /**
 * Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock,
@@ -80,11 +78,7 @@ uint32_t cy_Hfclk0FreqHz  = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT;
 uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
 
 /** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */
-#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN)
-    uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ;
-#else
-    uint32_t cy_BleEcoClockFreqHz = 0UL;
-#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */
+uint32_t cy_BleEcoClockFreqHz = 0UL;
 
 
 /*******************************************************************************
@@ -160,15 +154,11 @@ void SystemInit(void)
     Cy_SystemInit();
     SystemCoreClockUpdate();
 
-#if defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE)
-    if (CY_SYSLIB_DEVICE_REV_0A == Cy_SysLib_GetDeviceRevision())
-    {
-        /* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */
-        IPC_STRUCT7->DATA = 0UL;
-        /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
-        IPC_STRUCT7->RELEASE = 0UL;
-    }
-#endif /* defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) */
+    /* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */
+    REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL;
+
+    /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
+    REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL;
 
 #if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
     /* Allocate and initialize semaphores for the system operations. */
@@ -222,10 +212,7 @@ void SystemInit(void)
     /* .userPipeIsrHandler       */  &Cy_SysIpcPipeIsrCm0
     };
 
-    if (cy_device->flashPipeRequired != 0u)
-    {
-        Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0);
-    }
+    Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0);
 
 #if defined(CY_DEVICE_PSOC6ABLE2)
     Cy_Flash_Init();

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct

@@ -4,7 +4,7 @@
 
 ;*******************************************************************************
 ;* \file cy8c6xx7_cm4_dual.sct
-;* \version 2.60
+;* \version 2.70
 ;*
 ;* Linker file for the ARMCC.
 ;*
@@ -42,7 +42,7 @@
 ;* limitations under the License.
 ;******************************************************************************/
 
-; Size of the Cortex-M0+ application flash image
+; The size of the Cortex-M0+ application flash image
 #define FLASH_CM0P_SIZE     0x2000
 
 #if !defined(MBED_ROM_START)
@@ -82,7 +82,7 @@
   #define MBED_BOOT_STACK_SIZE 0x400
 #endif
 
-; Size of the stack section at the end of CM4 SRAM
+; The size of the stack section at the end of CM4 SRAM
 #define STACK_SIZE MBED_BOOT_STACK_SIZE
 
 ; The defines below describe the location and size of blocks of memory in the target.

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S

@@ -23,7 +23,6 @@
 ; * limitations under the License.
 ; */
 
-
                 PRESERVE8
                 THUMB
 
@@ -633,7 +632,6 @@ pass_interrupt_dacs_IRQHandler
 
                 ALIGN
 
-
                 END
 
 

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld

@@ -1,6 +1,6 @@
 /***************************************************************************//**
 * \file cy8c6xx7_cm4_dual.ld
-* \version 2.60
+* \version 2.70
 *
 * Linker file for the GNU C compiler.
 *
@@ -40,7 +40,7 @@ SEARCH_DIR(.)
 GROUP(-lgcc -lc -lnosys)
 ENTRY(Reset_Handler)
 
-/* Size of the Cortex-M0+ application image at the start of FLASH */
+/* The size of the Cortex-M0+ application image at the start of FLASH */
 FLASH_CM0P_SIZE = 0x2000;
 
 #if !defined(MBED_ROM_START)
@@ -79,7 +79,7 @@ FLASH_CM0P_SIZE = 0x2000;
     #define MBED_BOOT_STACK_SIZE 0x400
 #endif
 
-/* Size of the stack section at the end of CM4 SRAM */
+/* The size of the stack section at the end of CM4 SRAM */
 STACK_SIZE = MBED_BOOT_STACK_SIZE;
 
 /* Force symbol to be entered in the output file as an undefined symbol. Doing

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf

@@ -1,6 +1,6 @@
 /***************************************************************************//**
 * \file cy8c6xx7_cm4_dual.icf
-* \version 2.60
+* \version 2.70
 *
 * Linker file for the IAR compiler.
 *
@@ -41,7 +41,7 @@
 /*-Specials-*/
 define symbol __ICFEDIT_intvec_start__ = 0x00000000;
 
-/* Size of the Cortex-M0+ application image */
+/* The size of the Cortex-M0+ application image */
 define symbol FLASH_CM0P_SIZE  = 0x2000;
 
 if (!isdefinedsymbol(MBED_ROM_START)) {
@@ -108,7 +108,7 @@ define symbol __ICFEDIT_region_IROM0_end__   = (MBED_ROM_START + FLASH_CM0P_SIZE
 define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START;
 define symbol __ICFEDIT_region_IROM1_end__   = (MBED_APP_START + MBED_APP_SIZE);
 
-/* The following symbols define a 32K flash region used for EEPROM emulation. 
+/* The following symbols define a 32K flash region used for EEPROM emulation.
  * This region can also be used as the general purpose flash.
  * You can assign sections to this memory region for only one of the cores.
  * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S

@@ -310,10 +310,6 @@ intvec_copy
         STR r0, [r1]
         dsb
 
-        ; Enable the FPU if used
-        LDR     R0, =Cy_SystemInitFpuEnable
-        BLX     R0
-
         ; Initialize data sections
         LDR     R0, =__iar_data_init3
         BLX     R0