Final source code cleanup. Smaller changes in system_msp432p401r.c

Andreas Terstegge · Andreas Terstegge · commit e16394cf098a · 2019-09-03T11:19:32.000+02:00
diff --git a/targets/TARGET_TI/TARGET_MSP432/PeripheralNames.h b/targets/TARGET_TI/TARGET_MSP432/PeripheralNames.h
@@ -29,7 +29,7 @@
  * to integers...
  */
 
-#define DEVICE_SPI_COUNT 4
+#define DEVICE_SPI_COUNT 8
 
 typedef uint32_t ADCName;
 typedef uint32_t UARTName;
diff --git a/targets/TARGET_TI/TARGET_MSP432/TARGET_MSP432P401R/device/TOOLCHAIN_ARM_STD/msp432p401r.sct b/targets/TARGET_TI/TARGET_MSP432/TARGET_MSP432P401R/device/TOOLCHAIN_ARM_STD/msp432p401r.sct
@@ -1,5 +1,9 @@
 #! armcc -E
 
+/**********************************************************
+ * ARM CC  linker script for Texas Instruments MSP432P401R
+ **********************************************************/
+
 /* Device specific values */
 
 #define ROM_START   0x00000000
diff --git a/targets/TARGET_TI/TARGET_MSP432/TARGET_MSP432P401R/device/TOOLCHAIN_IAR/msp432p401r.icf b/targets/TARGET_TI/TARGET_MSP432/TARGET_MSP432P401R/device/TOOLCHAIN_IAR/msp432p401r.icf
@@ -1,3 +1,7 @@
+/******************************************************
+ * IAR linker script for Texas Instruments MSP432P401R
+ ******************************************************/
+
 /* Device specific values */
 
 define symbol ROM_START   = 0x00000000;
diff --git a/targets/TARGET_TI/TARGET_MSP432/TARGET_MSP432P401R/device/startup_msp432p401r.c b/targets/TARGET_TI/TARGET_MSP432/TARGET_MSP432P401R/device/startup_msp432p401r.c
@@ -228,7 +228,8 @@ void (* const interruptVectors[])(void) __attribute__((section(".isr_vector")))
 void Reset_Handler(void)
 {
     // Halt the WDT already here, because the following copy process
-    // from flash to SRAM might take so long that the WDT kicks in
+    // from flash to SRAM (in case of GCC) might take so long that the
+    // WDT kicks in
     WDT_A->CTL = WDT_A_CTL_PW | WDT_A_CTL_HOLD;
 #if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
     // Call system initialization routine
diff --git a/targets/TARGET_TI/TARGET_MSP432/TARGET_MSP432P401R/device/system_msp432p401r.c b/targets/TARGET_TI/TARGET_MSP432/TARGET_MSP432P401R/device/system_msp432p401r.c
@@ -29,14 +29,7 @@
 #define __REFOCLK_H 128000
 #define __SYSCLK    5000000
 
-// We currently do not support a DCO frequency of 1.5MHz, because the SMCLK
-// should be at least at 3MHz because of the uTicker, which needs 1MHz.
-// SMCLK is typically the half of MCLK. The longest PWM periods depend on
-// SMCLK: Timer A is only 16 bit and has a maximum pre-scaler of 64, so the
-// longest PWM period is:
-// With SMCLK =  3MHz, the maximum period is 1.39s.
-// With SMCLK = 24MHz, the maximum period is (only) 174.8ms
-
+// Configuration items in targets.json
 #define DCO_1500kHz 0
 #define DCO_3MHz    1
 #define DCO_6MHz    2
@@ -101,7 +94,7 @@
 #elif (MBED_CONF_TARGET_MCLK_SELECT == REFO)
 #define __MASTER_CLOCK (__REFOCLK_L / MCLK_DIVIDER)
 #elif (MBED_CONF_TARGET_MCLK_SELECT == DCO)
-#define __MASTER_CLOCK ( (3000000 << (MBED_CONF_TARGET_DCO_RSEL-1)) / MCLK_DIVIDER)
+#define __MASTER_CLOCK ( (1500000 << MBED_CONF_TARGET_DCO_RSEL) / MCLK_DIVIDER)
 #elif (MBED_CONF_TARGET_MCLK_SELECT == MOD)
 #define __MASTER_CLOCK (__MODCLK / MCLK_DIVIDER)
 #elif (MBED_CONF_TARGET_MCLK_SELECT == HFXT)
@@ -118,7 +111,7 @@
 #elif (MBED_CONF_TARGET_MCLK_SELECT == REFO)
 #define __SUBSYS_CLOCK (__REFOCLK_L / SMCLK_DIVIDER)
 #elif (MBED_CONF_TARGET_MCLK_SELECT == DCO)
-#define __SUBSYS_CLOCK ( (3000000 << (MBED_CONF_TARGET_DCO_RSEL-1)) / SMCLK_DIVIDER)
+#define __SUBSYS_CLOCK ((1500000 << MBED_CONF_TARGET_DCO_RSEL) / SMCLK_DIVIDER)
 #elif (MBED_CONF_TARGET_MCLK_SELECT == MOD)
 #define __SUBSYS_CLOCK (__MODCLK / SMCLK_DIVIDER)
 #elif (MBED_CONF_TARGET_MCLK_SELECT == HFXT)
@@ -127,10 +120,16 @@
 #error No SMCLK source defined (MBED_CONF_TARGET_SMCLK_SELECT)
 #endif
 
-// global clock variables
+// Global clock variables
 uint32_t SystemCoreClock      = __MASTER_CLOCK;  // the value of MCLK in Hz
 uint32_t SubsystemMasterClock = __SUBSYS_CLOCK;  // the value of SMCLK in Hz
 
+// Global xtal frequencies. If the xtal oscillators are enabled
+// during run-time, the frequencies have to be set here so that
+// SystemCoreClockUpdate can use them.
+uint32_t HfxtFrequency = 0;
+uint32_t LfxtFrequency = 0;
+
 //
 // Initialize the system
 //
@@ -144,7 +143,8 @@ uint32_t SubsystemMasterClock = __SUBSYS_CLOCK;  // the value of SMCLK in Hz
 //     2. Enables all SRAM banks
 //     3. Sets up power regulator and VCORE
 //     4. Enable Flash wait states if needed and read buffering
-//     5. Change MCLK/SMCLK to desired frequency
+//     5. Enable HFXT and/or LFXT if needed
+//     6. Configure the Clock System (CS)
 //
 void SystemInit(void)
 {
@@ -153,9 +153,6 @@ void SystemInit(void)
     // Enable all SRAM banks
     SYSCTL->SRAM_BANKEN = SYSCTL_SRAM_BANKEN_BNK7_EN;
 
-    // Unlock CS module
-    CS->KEY = CS_KEY_VAL;
-
 #if (__MASTER_CLOCK >= 48000000)
     // Switches to DCDC VCORE1
     while ((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
@@ -164,21 +161,26 @@ void SystemInit(void)
     // 1 flash wait states (BANK0 VCORE1 max is 16 MHz,
     // BANK1 VCORE1 max is 32 MHz)
     FLCTL->BANK0_RDCTL = FLCTL_BANK0_RDCTL_WAIT_1 | FLCTL_BANK0_RDCTL_BUFD
-                         | FLCTL_BANK0_RDCTL_BUFI;
+                                                  | FLCTL_BANK0_RDCTL_BUFI;
     FLCTL->BANK1_RDCTL = FLCTL_BANK1_RDCTL_WAIT_1 | FLCTL_BANK1_RDCTL_BUFD
-                         | FLCTL_BANK1_RDCTL_BUFI;
+                                                  | FLCTL_BANK1_RDCTL_BUFI;
 #elif (__MASTER_CLOCK >= 24000000)
     // Switches to DCDC VCORE0
     while ((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
     PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR__AM_DCDC_VCORE0;
     while ((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
     // Enable read buffering and 1 flash wait state (BANK0 VCORE0 max is 12 MHz)
     FLCTL->BANK0_RDCTL = FLCTL_BANK0_RDCTL_WAIT_1 | FLCTL_BANK0_RDCTL_BUFD
-                         | FLCTL_BANK0_RDCTL_BUFI;
+                                                  | FLCTL_BANK0_RDCTL_BUFI;
 #endif
 
-#if ((MBED_CONF_TARGET_MCLK_SELECT == HFXT) || (MBED_CONF_TARGET_SMCLK_SELECT == HFXT))
-    // initialize PJ.2 and PJ.3 for HFXT
+    // Unlock CS module
+    CS->KEY = CS_KEY_VAL;
+
+#ifdef MBED_CONF_TARGET_HFXT_HZ
+    HfxtFrequency = MBED_CONF_TARGET_HFXT_HZ;
+    // Enable the HFXT crystal oscillator.
+    // Initialize PJ for HFXT
     PJ->SEL0 |=  BIT3;
     PJ->SEL1 &= ~BIT3;
     CS->CTL2 |= CS_CTL2_HFXT_EN | HFXT_FREQ;
@@ -188,20 +190,12 @@ void SystemInit(void)
     }
 #endif
 
-    // Set CTL0 and CTL1
-    CS->CTL0 =(MBED_CONF_TARGET_DCO_RSEL     << CS_CTL0_DCORSEL_OFS) |
-              (MBED_CONF_TARGET_DCO_TUNE & 0x3ff);
-    CS->CTL1 = MBED_CONF_TARGET_MCLK_SELECT  << CS_CTL1_SELM_OFS |
-               MBED_CONF_TARGET_MCLK_DIV     << CS_CTL1_DIVM_OFS |
-               MBED_CONF_TARGET_SMCLK_SELECT << CS_CTL1_SELS_OFS |
-               MBED_CONF_TARGET_SMCLK_DIV    << CS_CTL1_DIVS_OFS;
-
 #ifdef MBED_CONF_TARGET_LFXT_HZ
-    // Configure the 32768Hz source. If the LFXT is not
+    LfxtFrequency = MBED_CONF_TARGET_LFXT_HZ;
+    // Enable the LFXT crystal oscillator. If the LFXT is not
     // available, the system will switch automatically to
-    // REFOCLK with 32768Hz mode (less precision...)
-
-    // initialize PJ.0 and PJ.1 for LFXT
+    // REFOCLK with 32768Hz mode (less precision...).
+    // Initialize PJ for LFXT
     PJ->SEL0 |=  BIT0;
     PJ->SEL1 &= ~BIT0;
     // Enable LFXT
@@ -212,9 +206,18 @@ void SystemInit(void)
     }
 #endif
 
+    // Set CTL0 and CTL1
+    CS->CTL0 =(MBED_CONF_TARGET_DCO_RSEL     << CS_CTL0_DCORSEL_OFS) |
+              (MBED_CONF_TARGET_DCO_TUNE & 0x3ff);
+    CS->CTL1 = MBED_CONF_TARGET_MCLK_SELECT  << CS_CTL1_SELM_OFS |
+               MBED_CONF_TARGET_MCLK_DIV     << CS_CTL1_DIVM_OFS |
+               MBED_CONF_TARGET_SMCLK_SELECT << CS_CTL1_SELS_OFS |
+               MBED_CONF_TARGET_SMCLK_DIV    << CS_CTL1_DIVS_OFS;
+
     // Lock CS module
     CS->KEY = 0;
-    // Update the global clock values
+
+    // Update the global clock values.
     SystemCoreClockUpdate();
 }
 
@@ -247,9 +250,7 @@ void SystemCoreClockUpdate(void)
                 // always switch to REFOCLK with 32768Hz
                 SystemCoreClock = __REFOCLK_L;
             } else {
-#ifdef MBED_CONF_TARGET_LFXT_HZ
-                SystemCoreClock = MBED_CONF_TARGET_LFXT_HZ;
-#endif
+                SystemCoreClock = LfxtFrequency;
             }
             break;
         }
@@ -335,9 +336,7 @@ void SystemCoreClockUpdate(void)
                 // switch over to SYSOSC...
                 SystemCoreClock = __SYSCLK;
             } else {
-#ifdef MBED_CONF_TARGET_HFXT_HZ            
-                SystemCoreClock = MBED_CONF_TARGET_HFXT_HZ;
-#endif
+                SystemCoreClock = HfxtFrequency;
             }
             break;
         }
@@ -357,9 +356,7 @@ void SystemCoreClockUpdate(void)
                 // always switch to REFOCLK with 32768Hz
                 SubsystemMasterClock = __REFOCLK_L;
             } else {
-#ifdef MBED_CONF_TARGET_LFXT_HZ            
-                SubsystemMasterClock = MBED_CONF_TARGET_LFXT_HZ;
-#endif
+                SubsystemMasterClock = LfxtFrequency;
             }
             break;
         }
@@ -445,9 +442,7 @@ void SystemCoreClockUpdate(void)
                 // switch over to SYSOSC...
                 SubsystemMasterClock = __SYSCLK;
             } else {
-#ifdef MBED_CONF_TARGET_HFXT_HZ            
-                SubsystemMasterClock = MBED_CONF_TARGET_HFXT_HZ;
-#endif                
+                SubsystemMasterClock = HfxtFrequency;
             }
             break;
         }
diff --git a/targets/TARGET_TI/TARGET_MSP432/device/cmsis.h b/targets/TARGET_TI/TARGET_MSP432/device/cmsis.h
@@ -21,7 +21,6 @@
 #undef DIR_H
 
 #include "msp.h"
-#include "cmsis_nvic.h"
 
 #undef CS
 
diff --git a/targets/TARGET_TI/TARGET_MSP432/device/cmsis_nvic.h b/targets/TARGET_TI/TARGET_MSP432/device/cmsis_nvic.h
diff --git a/targets/TARGET_TI/TARGET_MSP432/i2c_api.c b/targets/TARGET_TI/TARGET_MSP432/i2c_api.c
@@ -15,7 +15,10 @@
  * limitations under the License.
  */
 
-/* Low-level implementation of I2C functionality for MSP432 */
+/* Low-level implementation of I2C functionality for MSP432.
+ * This implementation does also support DEVICE_I2CSLAVE and DEVICE_I2C_ASYNCH.
+ */
+
 
 #if DEVICE_I2C
 
diff --git a/targets/TARGET_TI/TARGET_MSP432/objects.h b/targets/TARGET_TI/TARGET_MSP432/objects.h
@@ -80,7 +80,7 @@ struct spi_s {
     PinName pin_mosi;
     PinName pin_sclk;
     PinName pin_ssel;
-    // Addresses of needed HW-registers
+    // Addresses of HW-registers
     __IO uint16_t *EUSCI_CTLW0;
     __IO uint16_t *EUSCI_BRW;
     __IO uint16_t *EUSCI_STATW;
diff --git a/targets/TARGET_TI/TARGET_MSP432/spi_api.c b/targets/TARGET_TI/TARGET_MSP432/spi_api.c
@@ -15,22 +15,15 @@
  * limitations under the License.
  */
 
+/* Low-level implementation of SPI functionality for MSP432.
+ * This implementation does also support DEVICE_SPISLAVE and DEVICE_SPI_ASYNCH.
+ */
+
 #include "spi_api.h"
 #include "mbed_assert.h"
 
 #if DEVICE_SPI
 
-//#define SPI_EVENT_ERROR       (1 << 1)
-//#define SPI_EVENT_COMPLETE    (1 << 2)
-//#define SPI_EVENT_RX_OVERFLOW (1 << 3)
-//#define SPI_EVENT_ALL         (SPI_EVENT_ERROR | SPI_EVENT_COMPLETE | SPI_EVENT_RX_OVERFLOW)
-//
-//#define SPI_EVENT_INTERNAL_TRANSFER_COMPLETE (1 << 30) // Internal flag to report that an event occurred
-//
-//#define SPI_FILL_WORD         (0xFFFF)
-//#define SPI_FILL_CHAR         (0xFF)
-
-
 /* With SPI_ASYNCH, our type spi_s is embedded
  * into a bigger structure (see spi_api.h). So we
  * need a macro to extract the spi_s object.
