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30 | 30 | #include "PeripheralNames.h" |
31 | 31 | #include "stm32f4xx_hal.h" |
32 | 32 |
|
33 | | -// Timer selection: |
34 | | -#define TIM_MST TIM1 |
35 | | -#define TIM_MST_UP_IRQ TIM1_UP_TIM10_IRQn |
36 | | -#define TIM_MST_OC_IRQ TIM1_CC_IRQn |
37 | | -#define TIM_MST_RCC __TIM1_CLK_ENABLE() |
| 33 | +// 32-bit timer selection |
| 34 | +#define TIM_MST TIM5 |
| 35 | +#define TIM_MST_IRQ TIM5_IRQn |
| 36 | +#define TIM_MST_RCC __TIM5_CLK_ENABLE() |
38 | 37 |
|
39 | 38 | static TIM_HandleTypeDef TimMasterHandle; |
40 | | - |
41 | | -static int us_ticker_inited = 0; |
42 | | -static volatile uint32_t SlaveCounter = 0; |
43 | | -static volatile uint32_t oc_int_part = 0; |
44 | | -static volatile uint16_t oc_rem_part = 0; |
45 | | - |
46 | | -void set_compare(uint16_t count) { |
47 | | - // Set new output compare value |
48 | | - __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_1, count); |
49 | | - // Enable IT |
50 | | - __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC1); |
51 | | -} |
52 | | - |
53 | | -// Used to increment the slave counter |
54 | | -static void tim_update_irq_handler(void) { |
55 | | - if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_UPDATE) == SET) { |
56 | | - __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_UPDATE); |
57 | | - __HAL_TIM_SetCounter(&TimMasterHandle, 0); // Reset counter !!! |
58 | | - SlaveCounter++; |
59 | | - } |
60 | | -} |
61 | | - |
62 | | -// Used by interrupt system |
63 | | -static void tim_oc_irq_handler(void) { |
64 | | - uint16_t cval = TIM_MST->CNT; |
65 | | - |
66 | | - // Clear interrupt flag |
67 | | - if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC1) == SET) { |
68 | | - __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC1); |
69 | | - } |
70 | | - |
71 | | - if (oc_rem_part > 0) { |
72 | | - set_compare(oc_rem_part); // Finish the remaining time left |
73 | | - oc_rem_part = 0; |
74 | | - } |
75 | | - else { |
76 | | - if (oc_int_part > 0) { |
77 | | - set_compare(0xFFFF); |
78 | | - oc_rem_part = cval; // To finish the counter loop the next time |
79 | | - oc_int_part--; |
80 | | - } |
81 | | - else { |
82 | | - us_ticker_irq_handler(); |
83 | | - } |
84 | | - } |
85 | | -} |
| 39 | +static int us_ticker_inited = 0; |
86 | 40 |
|
87 | 41 | void us_ticker_init(void) { |
88 | 42 | if (us_ticker_inited) return; |
89 | 43 | us_ticker_inited = 1; |
90 | 44 |
|
91 | | - // Enable Timer clock |
| 45 | + // Enable timer clock |
92 | 46 | TIM_MST_RCC; |
93 | 47 |
|
94 | 48 | // Configure time base |
95 | 49 | TimMasterHandle.Instance = TIM_MST; |
96 | | - TimMasterHandle.Init.Period = 0xFFFF; |
| 50 | + TimMasterHandle.Init.Period = 0xFFFFFFFF; |
97 | 51 | TimMasterHandle.Init.Prescaler = (uint32_t)(SystemCoreClock / 1000000) - 1; // 1 µs tick |
98 | 52 | TimMasterHandle.Init.ClockDivision = 0; |
99 | 53 | TimMasterHandle.Init.CounterMode = TIM_COUNTERMODE_UP; |
100 | 54 | TimMasterHandle.Init.RepetitionCounter = 0; |
101 | 55 | HAL_TIM_OC_Init(&TimMasterHandle); |
102 | | - |
103 | | - // Configure interrupts |
104 | | - __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_UPDATE); |
105 | | - |
106 | | - // Update interrupt used for 32-bit counter |
107 | | - NVIC_SetVector(TIM_MST_UP_IRQ, (uint32_t)tim_update_irq_handler); |
108 | | - NVIC_EnableIRQ(TIM_MST_UP_IRQ); |
109 | 56 |
|
110 | | - // Output compare interrupt used for timeout feature |
111 | | - NVIC_SetVector(TIM_MST_OC_IRQ, (uint32_t)tim_oc_irq_handler); |
112 | | - NVIC_EnableIRQ(TIM_MST_OC_IRQ); |
| 57 | + NVIC_SetVector(TIM_MST_IRQ, (uint32_t)us_ticker_irq_handler); |
| 58 | + NVIC_EnableIRQ(TIM_MST_IRQ); |
113 | 59 |
|
114 | 60 | // Enable timer |
115 | 61 | HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_1); |
116 | 62 | } |
117 | 63 |
|
118 | 64 | uint32_t us_ticker_read() { |
119 | | - uint32_t counter, counter2; |
120 | 65 | if (!us_ticker_inited) us_ticker_init(); |
121 | | - // A situation might appear when Master overflows right after Slave is read and before the |
122 | | - // new (overflowed) value of Master is read. Which would make the code below consider the |
123 | | - // previous (incorrect) value of Slave and the new value of Master, which would return a |
124 | | - // value in the past. Avoid this by computing consecutive values of the timer until they |
125 | | - // are properly ordered. |
126 | | - counter = (uint32_t)(SlaveCounter << 16); |
127 | | - counter += TIM_MST->CNT; |
128 | | - while (1) { |
129 | | - counter2 = (uint32_t)(SlaveCounter << 16); |
130 | | - counter2 += TIM_MST->CNT; |
131 | | - if (counter2 > counter) { |
132 | | - break; |
133 | | - } |
134 | | - counter = counter2; |
135 | | - } |
136 | | - return counter2; |
| 66 | + return TIM_MST->CNT; |
137 | 67 | } |
138 | 68 |
|
139 | 69 | void us_ticker_set_interrupt(unsigned int timestamp) { |
140 | | - int delta = (int)(timestamp - us_ticker_read()); |
141 | | - uint16_t cval = TIM_MST->CNT; |
142 | | - |
143 | | - if (delta <= 0) { // This event was in the past |
144 | | - us_ticker_irq_handler(); |
145 | | - } |
146 | | - else { |
147 | | - oc_int_part = (uint32_t)(delta >> 16); |
148 | | - oc_rem_part = (uint16_t)(delta & 0xFFFF); |
149 | | - if (oc_rem_part <= (0xFFFF - cval)) { |
150 | | - set_compare(cval + oc_rem_part); |
151 | | - oc_rem_part = 0; |
152 | | - } else { |
153 | | - set_compare(0xFFFF); |
154 | | - oc_rem_part = oc_rem_part - (0xFFFF - cval); |
155 | | - } |
156 | | - } |
| 70 | + // Set new output compare value |
| 71 | + __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_1, timestamp); |
| 72 | + // Enable IT |
| 73 | + __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC1); |
157 | 74 | } |
158 | 75 |
|
159 | 76 | void us_ticker_disable_interrupt(void) { |
160 | 77 | __HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC1); |
161 | 78 | } |
162 | 79 |
|
163 | 80 | void us_ticker_clear_interrupt(void) { |
164 | | - if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC1) == SET) { |
165 | | - __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC1); |
166 | | - } |
| 81 | + __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC1); |
167 | 82 | } |
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