@@ -173,7 +173,7 @@ static nordic_uart_state_t nordic_nrf5_uart_state[NRFX_UARTE_ENABLED_COUNT] = {
173173 */
174174static NRF_UARTE_Type * nordic_nrf5_uart_register [NRFX_UARTE_ENABLED_COUNT ] = {
175175 NRF_UARTE0 ,
176- #if UART1_ENABLED
176+ #if NRFX_UARTE1_ENABLED
177177 NRF_UARTE1 ,
178178#endif
179179};
@@ -184,7 +184,7 @@ static NRF_UARTE_Type *nordic_nrf5_uart_register[NRFX_UARTE_ENABLED_COUNT] = {
184184 */
185185NRF_ATFIFO_DEF (nordic_nrf5_uart_fifo_0 , uint8_t , UART0_FIFO_BUFFER_SIZE );
186186
187- #if UART1_ENABLED
187+ #if NRFX_UARTE1_ENABLED
188188NRF_ATFIFO_DEF (nordic_nrf5_uart_fifo_1 , uint8_t , UART1_FIFO_BUFFER_SIZE );
189189#endif
190190
@@ -193,7 +193,7 @@ NRF_ATFIFO_DEF(nordic_nrf5_uart_fifo_1, uint8_t, UART1_FIFO_BUFFER_SIZE);
193193 */
194194static uint8_t nordic_nrf5_uart_swi_mask_tx_0 = 0 ;
195195static uint8_t nordic_nrf5_uart_swi_mask_rx_0 = 0 ;
196- #if UART1_ENABLED
196+ #if NRFX_UARTE1_ENABLED
197197static uint8_t nordic_nrf5_uart_swi_mask_tx_1 = 0 ;
198198static uint8_t nordic_nrf5_uart_swi_mask_rx_1 = 0 ;
199199#endif
@@ -313,7 +313,7 @@ static void nordic_nrf5_uart_swi0(void)
313313 }
314314
315315
316- #if UART1_ENABLED
316+ #if NRFX_UARTE1_ENABLED
317317 if (nordic_nrf5_uart_swi_mask_tx_1 ) {
318318
319319 nordic_nrf5_uart_swi_mask_tx_1 = 0 ;
@@ -350,7 +350,7 @@ static void nordic_swi_tx_trigger(int instance)
350350 nordic_nrf5_uart_swi_mask_tx_0 = 1 ;
351351 NVIC_SetPendingIRQ (SWI0_EGU0_IRQn );
352352 }
353- #if UART1_ENABLED
353+ #if NRFX_UARTE1_ENABLED
354354 else if (instance == 1 ) {
355355
356356 nordic_nrf5_uart_swi_mask_tx_1 = 1 ;
@@ -371,7 +371,7 @@ static void nordic_swi_rx_trigger(int instance)
371371 nordic_nrf5_uart_swi_mask_rx_0 = 1 ;
372372 NVIC_SetPendingIRQ (SWI0_EGU0_IRQn );
373373 }
374- #if UART1_ENABLED
374+ #if NRFX_UARTE1_ENABLED
375375 else if (instance == 1 ) {
376376
377377 nordic_nrf5_uart_swi_mask_rx_1 = 1 ;
@@ -554,7 +554,7 @@ static void nordic_nrf5_uart0_handler(void)
554554 nordic_nrf5_uart_event_handler (0 );
555555}
556556
557- #if UART1_ENABLED
557+ #if NRFX_UARTE1_ENABLED
558558/**
559559 * @brief UARTE1 ISR.
560560 */
@@ -876,7 +876,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx)
876876 NRFX_IRQ_PRIORITY_SET (UARTE0_UART0_IRQn , APP_IRQ_PRIORITY_HIGHEST );
877877 NRFX_IRQ_ENABLE (UARTE0_UART0_IRQn );
878878
879- #if UART1_ENABLED
879+ #if NRFX_UARTE1_ENABLED
880880 /* Initialize FIFO buffer for UARTE1. */
881881 NRF_ATFIFO_INIT (nordic_nrf5_uart_fifo_1 );
882882 nordic_nrf5_uart_state [1 ].fifo = nordic_nrf5_uart_fifo_1 ;
@@ -1015,7 +1015,7 @@ void serial_free(serial_t *obj)
10151015 * (volatile uint32_t * )0x40002FFC ;
10161016 * (volatile uint32_t * )0x40002FFC = 1 ;
10171017 }
1018- #if UART1_ENABLED
1018+ #if NRFX_UARTE1_ENABLED
10191019 else {
10201020 * (volatile uint32_t * )0x40028FFC = 0 ;
10211021 * (volatile uint32_t * )0x40028FFC ;
@@ -1505,7 +1505,7 @@ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx
15051505 valid = true;
15061506 }
15071507 }
1508- #if UART1_ENABLED
1508+ #if NRFX_UARTE1_ENABLED
15091509 else {
15101510 if (nrfx_is_in_ram (tx ) || (tx_length <= UART1_FIFO_BUFFER_SIZE )) {
15111511 valid = true;
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