M487, NUC472 EMAC code fulfill astyle

Author: cyliangtw

features/netsocket/emac-drivers/TARGET_NUVOTON_EMAC/TARGET_M480/m480_eth.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018 Nuvoton Technology Corp. 
+ * Copyright (c) 2018 Nuvoton Technology Corp.
  * Copyright (c) 2018 ARM Limited
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
@@ -28,18 +28,18 @@
 #define ETH_ENABLE_RX()     do{EMAC->CTL |= EMAC_CTL_RXON_Msk;}while(0)
 #define ETH_DISABLE_TX()    do{EMAC->CTL &= ~EMAC_CTL_TXON;}while(0)
 #define ETH_DISABLE_RX()    do{EMAC->CTL &= ~EMAC_CTL_RXON_Msk;}while(0)
-    
+
 #define EMAC_ENABLE_INT(emac, u32eIntSel)    ((emac)->INTEN |= (u32eIntSel))
-#define EMAC_DISABLE_INT(emac, u32eIntSel)    ((emac)->INTEN &= ~ (u32eIntSel))    
+#define EMAC_DISABLE_INT(emac, u32eIntSel)    ((emac)->INTEN &= ~ (u32eIntSel))
 
 MBED_ALIGN(4) struct eth_descriptor rx_desc[RX_DESCRIPTOR_NUM];
 MBED_ALIGN(4) struct eth_descriptor tx_desc[TX_DESCRIPTOR_NUM];
 
 struct eth_descriptor volatile *cur_tx_desc_ptr, *cur_rx_desc_ptr, *fin_tx_desc_ptr;
 
-__attribute__ ((section("EMAC_RAM")))
+__attribute__((section("EMAC_RAM")))
 MBED_ALIGN(4) uint8_t rx_buf[RX_DESCRIPTOR_NUM][PACKET_BUFFER_SIZE];
-__attribute__ ((section("EMAC_RAM")))
+__attribute__((section("EMAC_RAM")))
 MBED_ALIGN(4) uint8_t tx_buf[TX_DESCRIPTOR_NUM][PACKET_BUFFER_SIZE];
 
 eth_callback_t nu_eth_txrx_cb = NULL;
@@ -74,7 +74,7 @@ static uint16_t mdio_read(uint8_t addr, uint8_t reg)
     EMAC->MIIMCTL = (addr << EMAC_MIIMCTL_PHYADDR_Pos) | reg | EMAC_MIIMCTL_BUSY_Msk | EMAC_MIIMCTL_MDCON_Msk;
     while (EMAC->MIIMCTL & EMAC_MIIMCTL_BUSY_Msk);
 
-    return(EMAC->MIIMDAT);
+    return (EMAC->MIIMDAT);
 }
 
 static int reset_phy(void)
@@ -87,15 +87,18 @@ static int reset_phy(void)
     mdio_write(CONFIG_PHY_ADDR, MII_BMCR, BMCR_RESET);
 
     delayCnt = 2000;
-    while(delayCnt-- > 0) {
-        if((mdio_read(CONFIG_PHY_ADDR, MII_BMCR) & BMCR_RESET) == 0)
+
+    while (delayCnt > 0) {
+        delayCnt--;
+        if ((mdio_read(CONFIG_PHY_ADDR, MII_BMCR) & BMCR_RESET) == 0) {
             break;
+        }
 
     }
 
-    if(delayCnt == 0) {
+    if (delayCnt == 0) {
         NU_DEBUGF(("Reset phy failed\n"));
-        return(-1);
+        return (-1);
     }
 
     mdio_write(CONFIG_PHY_ADDR, MII_ADVERTISE, ADVERTISE_CSMA |
@@ -108,38 +111,41 @@ static int reset_phy(void)
     mdio_write(CONFIG_PHY_ADDR, MII_BMCR, reg | BMCR_ANRESTART);
 
     delayCnt = 200000;
-    while(delayCnt-- > 0) {
-        if((mdio_read(CONFIG_PHY_ADDR, MII_BMSR) & (BMSR_ANEGCOMPLETE | BMSR_LSTATUS))
-                == (BMSR_ANEGCOMPLETE | BMSR_LSTATUS))
+
+    while (delayCnt > 0) {
+        delayCnt--;
+        if ((mdio_read(CONFIG_PHY_ADDR, MII_BMSR) & (BMSR_ANEGCOMPLETE | BMSR_LSTATUS))
+                == (BMSR_ANEGCOMPLETE | BMSR_LSTATUS)) {
             break;
+        }
     }
 
-    if(delayCnt == 0) {
+    if (delayCnt == 0) {
         NU_DEBUGF(("AN failed. Set to 100 FULL\n"));
         EMAC->CTL |= (EMAC_CTL_OPMODE_Msk | EMAC_CTL_FUDUP_Msk);
-        return(-1);
+        return (-1);
     } else {
         reg = mdio_read(CONFIG_PHY_ADDR, MII_LPA);
         phyLPAval = reg;
 
-        if(reg & ADVERTISE_100FULL) {
+        if (reg & ADVERTISE_100FULL) {
             NU_DEBUGF(("100 full\n"));
             EMAC->CTL |= (EMAC_CTL_OPMODE_Msk | EMAC_CTL_FUDUP_Msk);
-        } else if(reg & ADVERTISE_100HALF) {
+        } else if (reg & ADVERTISE_100HALF) {
             NU_DEBUGF(("100 half\n"));
             EMAC->CTL = (EMAC->CTL & ~EMAC_CTL_FUDUP_Msk) | EMAC_CTL_OPMODE_Msk;
-        } else if(reg & ADVERTISE_10FULL) {
+        } else if (reg & ADVERTISE_10FULL) {
             NU_DEBUGF(("10 full\n"));
             EMAC->CTL = (EMAC->CTL & ~EMAC_CTL_OPMODE_Msk) | EMAC_CTL_FUDUP_Msk;
         } else {
             NU_DEBUGF(("10 half\n"));
             EMAC->CTL &= ~(EMAC_CTL_OPMODE_Msk | EMAC_CTL_FUDUP_Msk);
         }
     }
-	printf("PHY ID 1:0x%x\r\n", mdio_read(CONFIG_PHY_ADDR, MII_PHYSID1));
-	printf("PHY ID 2:0x%x\r\n", mdio_read(CONFIG_PHY_ADDR, MII_PHYSID2));
+    printf("PHY ID 1:0x%x\r\n", mdio_read(CONFIG_PHY_ADDR, MII_PHYSID1));
+    printf("PHY ID 2:0x%x\r\n", mdio_read(CONFIG_PHY_ADDR, MII_PHYSID2));
 
-    return(0);
+    return (0);
 }
 
 
@@ -150,7 +156,7 @@ static void init_tx_desc(void)
 
     cur_tx_desc_ptr = fin_tx_desc_ptr = &tx_desc[0];
 
-    for(i = 0; i < TX_DESCRIPTOR_NUM; i++) {
+    for (i = 0; i < TX_DESCRIPTOR_NUM; i++) {
         tx_desc[i].status1 = TXFD_PADEN | TXFD_CRCAPP | TXFD_INTEN;
         tx_desc[i].buf = &tx_buf[i][0];
         tx_desc[i].status2 = 0;
@@ -168,7 +174,7 @@ static void init_rx_desc(void)
 
     cur_rx_desc_ptr = &rx_desc[0];
 
-    for(i = 0; i < RX_DESCRIPTOR_NUM; i++) {
+    for (i = 0; i < RX_DESCRIPTOR_NUM; i++) {
         rx_desc[i].status1 = OWNERSHIP_EMAC;
         rx_desc[i].buf = &rx_buf[i][0];
         rx_desc[i].status2 = 0;
@@ -199,13 +205,13 @@ static void __eth_clk_pin_init()
 
     /* Enable IP clock */
     CLK_EnableModuleClock(EMAC_MODULE);
-    
+
     // Configure MDC clock rate to HCLK / (127 + 1) = 1.25 MHz if system is running at 160 MH
     CLK_SetModuleClock(EMAC_MODULE, 0, CLK_CLKDIV3_EMAC(127));
-    
+
     /* Update System Core Clock */
     SystemCoreClockUpdate();
-    
+
     /*---------------------------------------------------------------------------------------------------------*/
     /* Init I/O Multi-function                                                                                 */
     /*---------------------------------------------------------------------------------------------------------*/
@@ -219,10 +225,10 @@ static void __eth_clk_pin_init()
     SYS->GPE_MFPH &= ~(SYS_GPE_MFPH_PE8MFP_Msk | SYS_GPE_MFPH_PE9MFP_Msk | SYS_GPE_MFPH_PE10MFP_Msk |
                        SYS_GPE_MFPH_PE11MFP_Msk | SYS_GPE_MFPH_PE12MFP_Msk);
     SYS->GPE_MFPH |= SYS_GPE_MFPH_PE8MFP_EMAC_RMII_MDC |
-                    SYS_GPE_MFPH_PE9MFP_EMAC_RMII_MDIO |
-                    SYS_GPE_MFPH_PE10MFP_EMAC_RMII_TXD0 |
-                    SYS_GPE_MFPH_PE11MFP_EMAC_RMII_TXD1 |
-                    SYS_GPE_MFPH_PE12MFP_EMAC_RMII_TXEN;
+                     SYS_GPE_MFPH_PE9MFP_EMAC_RMII_MDIO |
+                     SYS_GPE_MFPH_PE10MFP_EMAC_RMII_TXD0 |
+                     SYS_GPE_MFPH_PE11MFP_EMAC_RMII_TXD1 |
+                     SYS_GPE_MFPH_PE12MFP_EMAC_RMII_TXEN;
 
     // Enable high slew rate on all RMII TX output pins
     PE->SLEWCTL = (GPIO_SLEWCTL_HIGH << GPIO_SLEWCTL_HSREN10_Pos) |
@@ -238,13 +244,13 @@ static void __eth_clk_pin_init()
 
 void numaker_eth_init(uint8_t *mac_addr)
 {
-    
-	// init CLK & pins
-	__eth_clk_pin_init();
-	
+
+    // init CLK & pins
+    __eth_clk_pin_init();
+
     // Reset MAC
     EMAC->CTL = EMAC_CTL_RST_Msk;
-    while(EMAC->CTL & EMAC_CTL_RST_Msk) {}
+    while (EMAC->CTL & EMAC_CTL_RST_Msk) {}
 
     init_tx_desc();
     init_rx_desc();
@@ -270,17 +276,15 @@ void numaker_eth_init(uint8_t *mac_addr)
     EMAC->CAMCTL =  EMAC_CAMCTL_CMPEN_Msk |
                     EMAC_CAMCTL_AMP_Msk |
                     EMAC_CAMCTL_ABP_Msk;
-    EMAC->CAMEN = 1;    // Enable CAM entry 0    
+    EMAC->CAMEN = 1;    // Enable CAM entry 0
     /* Limit the max receive frame length to 1514 + 4 */
     EMAC->MRFL = NU_ETH_MAX_FLEN;
-    
+
     /* Set RX FIFO threshold as 8 words */
     EMAC->FIFOCTL = 0x00200100;
-    
-    if (isPhyReset != true)
-    {
-        if (!reset_phy()) 
-        {
+
+    if (isPhyReset != true) {
+        if (!reset_phy()) {
             isPhyReset = true;
         }
     } else {
@@ -296,9 +300,9 @@ void numaker_eth_init(uint8_t *mac_addr)
         } else {
             NU_DEBUGF(("10 half\n"));
             EMAC->CTL &= ~(EMAC_CTL_OPMODE_Msk | EMAC_CTL_FUDUP_Msk);
-        }        
+        }
     }
-                    
+
     EMAC_ENABLE_RX();
     EMAC_ENABLE_TX();
 
@@ -321,11 +325,15 @@ void EMAC_RX_IRQHandler(void)
     if (m_status & EMAC_INTSTS_RXBEIF_Msk) {
         // Shouldn't goes here, unless descriptor corrupted
         mbed_error_printf("### RX Bus error [0x%x]\r\n", m_status);
-        if (nu_eth_txrx_cb != NULL) nu_eth_txrx_cb('B', nu_userData); 
+        if (nu_eth_txrx_cb != NULL) {
+            nu_eth_txrx_cb('B', nu_userData);
+        }
         return;
     }
     EMAC_DISABLE_INT(EMAC, (EMAC_INTEN_RDUIEN_Msk | EMAC_INTEN_RXGDIEN_Msk));
-	if (nu_eth_txrx_cb != NULL) nu_eth_txrx_cb('R', nu_userData); 
+    if (nu_eth_txrx_cb != NULL) {
+        nu_eth_txrx_cb('R', nu_userData);
+    }
 }
 
 
@@ -340,42 +348,48 @@ int numaker_eth_get_rx_buf(uint16_t *len, uint8_t **buf)
     unsigned int cur_entry, status;
 
     cur_entry = EMAC->CRXDSA;
-    if ((cur_entry == (uint32_t)cur_rx_desc_ptr) && (!(m_status & EMAC_INTSTS_RDUIF_Msk)))  // cur_entry may equal to cur_rx_desc_ptr if RDU occures
-            return -1;
+    if ((cur_entry == (uint32_t)cur_rx_desc_ptr) && (!(m_status & EMAC_INTSTS_RDUIF_Msk))) { // cur_entry may equal to cur_rx_desc_ptr if RDU occures
+        return -1;
+    }
     status = cur_rx_desc_ptr->status1;
 
-    if(status & OWNERSHIP_EMAC)
-            return -1;
+    if (status & OWNERSHIP_EMAC) {
+        return -1;
+    }
 
     if (status & RXFD_RXGD) {
         *buf = cur_rx_desc_ptr->buf;
         *len = status & 0xFFFF;
         // length of payload should be <= 1514
-        if ( *len > (NU_ETH_MAX_FLEN - 4) ) {
+        if (*len > (NU_ETH_MAX_FLEN - 4)) {
             NU_DEBUGF(("%s... unexpected long packet length=%d, buf=0x%x\r\n", __FUNCTION__, *len, *buf));
             *len = 0; // Skip this unexpected long packet
         }
-        if (*len == (NU_ETH_MAX_FLEN - 4)) NU_DEBUGF(("%s... length=%d, buf=0x%x\r\n", __FUNCTION__, *len, *buf));
+        if (*len == (NU_ETH_MAX_FLEN - 4)) {
+            NU_DEBUGF(("%s... length=%d, buf=0x%x\r\n", __FUNCTION__, *len, *buf));
+        }
     }
     return 0;
-}    
+}
 
 void numaker_eth_rx_next(void)
 {
     cur_rx_desc_ptr->status1 = OWNERSHIP_EMAC;
-    cur_rx_desc_ptr = cur_rx_desc_ptr->next;    
-}    
+    cur_rx_desc_ptr = cur_rx_desc_ptr->next;
+}
 
 void EMAC_TX_IRQHandler(void)
 {
     unsigned int cur_entry, status;
 
     status = EMAC->INTSTS & 0xFFFF0000;
     EMAC->INTSTS = status;
-    if(status & EMAC_INTSTS_TXBEIF_Msk) {
+    if (status & EMAC_INTSTS_TXBEIF_Msk) {
         // Shouldn't goes here, unless descriptor corrupted
         mbed_error_printf("### TX Bus error [0x%x]\r\n", status);
-        if (nu_eth_txrx_cb != NULL) nu_eth_txrx_cb('B', nu_userData); 
+        if (nu_eth_txrx_cb != NULL) {
+            nu_eth_txrx_cb('B', nu_userData);
+        }
         return;
     }
 
@@ -385,16 +399,19 @@ void EMAC_TX_IRQHandler(void)
 
         fin_tx_desc_ptr = fin_tx_desc_ptr->next;
     }
-    
-    if (nu_eth_txrx_cb != NULL) nu_eth_txrx_cb('T', nu_userData);
+
+    if (nu_eth_txrx_cb != NULL) {
+        nu_eth_txrx_cb('T', nu_userData);
+    }
 }
 
 uint8_t *numaker_eth_get_tx_buf(void)
 {
-    if(cur_tx_desc_ptr->status1 & OWNERSHIP_EMAC)
-        return(NULL);
-    else
-        return(cur_tx_desc_ptr->buf);
+    if (cur_tx_desc_ptr->status1 & OWNERSHIP_EMAC) {
+        return (NULL);
+    } else {
+        return (cur_tx_desc_ptr->buf);
+    }
 }
 
 void numaker_eth_trigger_tx(uint16_t length, void *p)
@@ -411,11 +428,12 @@ void numaker_eth_trigger_tx(uint16_t length, void *p)
 
 int numaker_eth_link_ok(void)
 {
-	/* first, a dummy read to latch */
-	mdio_read(CONFIG_PHY_ADDR, MII_BMSR);
-	if(mdio_read(CONFIG_PHY_ADDR, MII_BMSR) & BMSR_LSTATUS)
-		return 1;
-	return 0;	
+    /* first, a dummy read to latch */
+    mdio_read(CONFIG_PHY_ADDR, MII_BMSR);
+    if (mdio_read(CONFIG_PHY_ADDR, MII_BMSR) & BMSR_LSTATUS) {
+        return 1;
+    }
+    return 0;
 }
 
 void numaker_eth_set_cb(eth_callback_t eth_cb, void *userData)
@@ -437,43 +455,44 @@ void mbed_mac_address(char *mac)
     // http://en.wikipedia.org/wiki/MAC_address
     uint32_t word1 = *(uint32_t *)0x7F800; // 2KB Data Flash at 0x7F800
 
-	if( word0 == 0xFFFFFFFF )		// Not burn any mac address at 1st 2 words of Data Flash
-	{
+    if (word0 == 0xFFFFFFFF) {       // Not burn any mac address at 1st 2 words of Data Flash
         // with a semi-unique MAC address from the UUID
         /* Enable FMC ISP function */
         SYS_UnlockReg();
         FMC_Open();
         // = FMC_ReadUID(0);
         uID1 = FMC_ReadUID(1);
         word1 = (uID1 & 0x003FFFFF) | ((uID1 & 0x030000) << 6) >> 8;
-        word0 = ((FMC_ReadUID(0) >> 4) << 20) | ((uID1 & 0xFF)<<12) | (FMC_ReadUID(2) & 0xFFF);
+        word0 = ((FMC_ReadUID(0) >> 4) << 20) | ((uID1 & 0xFF) << 12) | (FMC_ReadUID(2) & 0xFFF);
         /* Disable FMC ISP function */
         FMC_Close();
         /* Lock protected registers */
         SYS_LockReg();
-	}
+    }
 
     word1 |= 0x00000200;
     word1 &= 0x0000FEFF;
 
-    mac[0] = (word1 & 0x0000ff00) >> 8;    
+    mac[0] = (word1 & 0x0000ff00) >> 8;
     mac[1] = (word1 & 0x000000ff);
     mac[2] = (word0 & 0xff000000) >> 24;
     mac[3] = (word0 & 0x00ff0000) >> 16;
     mac[4] = (word0 & 0x0000ff00) >> 8;
     mac[5] = (word0 & 0x000000ff);
-    
-    NU_DEBUGF(("mac address %02x-%02x-%02x-%02x-%02x-%02x \r\n", mac[0], mac[1],mac[2],mac[3],mac[4],mac[5]));
+
+    NU_DEBUGF(("mac address %02x-%02x-%02x-%02x-%02x-%02x \r\n", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]));
 }
 
-void numaker_eth_enable_interrupts(void) {
+void numaker_eth_enable_interrupts(void)
+{
     EMAC->INTEN |= EMAC_INTEN_RXIEN_Msk |
                    EMAC_INTEN_TXIEN_Msk ;
-	NVIC_EnableIRQ(EMAC_RX_IRQn);
-	NVIC_EnableIRQ(EMAC_TX_IRQn);
+    NVIC_EnableIRQ(EMAC_RX_IRQn);
+    NVIC_EnableIRQ(EMAC_TX_IRQn);
 }
 
-void numaker_eth_disable_interrupts(void) {
-	NVIC_DisableIRQ(EMAC_RX_IRQn);
-	NVIC_DisableIRQ(EMAC_TX_IRQn);
+void numaker_eth_disable_interrupts(void)
+{
+    NVIC_DisableIRQ(EMAC_RX_IRQn);
+    NVIC_DisableIRQ(EMAC_TX_IRQn);
 }