Rename 064B0S2 linker scripts names per common pattern

Author: romanjoe

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb8c6xxa_cm4_dual.sct renamed to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct

@@ -3,7 +3,7 @@
 ; to pass a scatter file through a C preprocessor.
 
 ;*******************************************************************************
-;* \file cy8bc6xxa_cm4_dual.sct
+;* \file cyb06xxa_cm4_dual.sct
 ;* \version 2.80
 ;*
 ;* Linker file for the ARMCC.
@@ -99,7 +99,7 @@
 ; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
 ; Using this memory region for other purposes will lead to unexpected behavior.
 ; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
+; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'.
 ; RAM
 #define RAM_START               MBED_RAM_START
 #define RAM_SIZE                MBED_RAM_SIZE

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld renamed to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4_dual.ld

@@ -1,5 +1,5 @@
 /***************************************************************************//**
-* \file cy8c6xxa_cm4_dual.ld
+* \file cyb06xxa_cm4_dual.ld
 * \version 2.80
 *
 * Linker file for the GNU C compiler.
@@ -40,13 +40,14 @@ SEARCH_DIR(.)
 GROUP(-lgcc -lc -lnosys)
 ENTRY(Reset_Handler)
 
-/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+/* By default, the COMPONENT_CM0P_SECURE prebuilt image is used for the CM0p core.
 * More about CM0+ prebuilt images, see here:
 * https://github.com/cypresssemiconductorco/psoc6cm0p
 */
 /* The size of the Cortex-M0+ application image at the start of FLASH */
 FLASH_CM0P_SIZE = 0x10000;
 
+/* The size of the MCU boot header area at the start of FLASH */
 BOOT_HEADER_SIZE = 0x400;
 
 #if !defined(MBED_ROM_START)
@@ -103,10 +104,9 @@ MEMORY
 {
     /* The ram and flash regions control RAM and flash memory allocation for the CM4 core.
      * You can change the memory allocation by editing the 'ram' and 'flash' regions.
-     * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
      * Using this memory region for other purposes will lead to unexpected behavior.
      * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld',
-     * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'.
+     * where 'xx' is the device group; for example, 'cyb06xxa_cm0plus.ld'.
      */
     ram               (rwx)   : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE
     cm0p_image        (rx)    : ORIGIN = (MBED_ROM_START + BOOT_HEADER_SIZE), LENGTH = FLASH_CM0P_SIZE

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cyb8c6xxa_cm4_dual.icf renamed to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4_dual.icf

@@ -1,5 +1,5 @@
 /*******************************************************************************
-* \file cyb8c6xxa_cm4_dual.icf
+* \file cyb06xxa_cm4_dual.icf
 * \version 2.80
 *
 * Linker file for the IAR compiler.
@@ -41,7 +41,7 @@
 /*-Specials-*/
 define symbol __ICFEDIT_intvec_start__ = 0x00000000;
 
-/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+/* By default, the COMPONENT_CM0P_SECURE prebuilt image is used for the CM0p core.
  * More about CM0+ prebuilt images, see here:
  * https://github.com/cypresssemiconductorco/psoc6cm0p
  */
@@ -103,7 +103,7 @@ define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
  * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
  * Using this memory region for other purposes will lead to unexpected behavior.
  * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf',
- * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'.
+ * where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.icf'.
  */
 /* RAM */
 define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START;