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PSOC6: cleanup DEVICE_QSPI mappings
Note: device_has: "QSPI" is still disabled for TARGET_PSOC6 (QSPI HAL implementation is incomplete).
1 parent 2524a67 commit bab34cb

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7 files changed

+74
-87
lines changed

7 files changed

+74
-87
lines changed

‎targets/TARGET_Cypress/TARGET_PSOC6/PeripheralPins.h‎

Lines changed: 2 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,7 @@
2424
#include "PeripheralNames.h"
2525

2626

27-
// //*** I2C ***
27+
//*** I2C ***
2828
#if DEVICE_I2C
2929
extern const PinMap PinMap_I2C_SDA[];
3030
extern const PinMap PinMap_I2C_SCL[];
@@ -51,13 +51,6 @@ extern const PinMap PinMap_SPI_SCLK[];
5151
extern const PinMap PinMap_SPI_SSEL[];
5252
#endif
5353

54-
//*** QSPI ***
55-
#if DEVICE_QSPI
56-
extern const PinMap PinMap_QSPI_SCLK[];
57-
extern const PinMap PinMap_QSPI_DATA[];
58-
extern const PinMap PinMap_QSPI_SSEL[];
59-
#endif
60-
6154
//*** ADC ***
6255
#if DEVICE_ANALOGIN
6356
extern const PinMap PinMap_ADC[];
@@ -68,6 +61,7 @@ extern const PinMap PinMap_ADC[];
6861
extern const PinMap PinMap_DAC[];
6962
#endif
7063

64+
//*** QSPI ***
7165
#if DEVICE_QSPI
7266
extern const PinMap PinMap_QSPI_SCLK[];
7367
extern const PinMap PinMap_QSPI_SSEL[];

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/PeripheralNames.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -108,8 +108,8 @@ typedef enum {
108108
} DACName;
109109

110110
typedef enum {
111-
SMIF_0 = (int)SMIF0_BASE,
112-
} SMIFName;
111+
QSPI_0,
112+
} QSPIName;
113113

114114
#ifdef __cplusplus
115115
}

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/PeripheralPins.c‎

Lines changed: 22 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -366,30 +366,28 @@ const PinMap PinMap_DAC[] = {
366366
#endif // DEVICE_ANALOGIN
367367

368368
#if DEVICE_QSPI
369-
const PinMap PinMap_QSPI_SCLK[] = { // does not use PERI clock, uses HFCLK2
370-
{P11_7, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_7_SMIF_SPI_CLK, 0)},
371-
{NC, NC, 0}
369+
const PinMap PinMap_QSPI_SCLK[] = {
370+
{P11_7, QSPI_0, CY_GPIO_CFG_CREATE(P11_7_SMIF_SPI_CLK, CY_GPIO_DM_STRONG_IN_OFF)},
371+
{NC, NC, 0},
372372
};
373-
374-
// Ensure that the spi_data pins are defined in the order 0 to 7
375-
const PinMap PinMap_QSPI_DATA[] = { // does not use PERI clock, uses HFCLK2
376-
{P11_6, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_6_SMIF_SPI_DATA0, 0)}, // spi_data0
377-
{P11_5, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_5_SMIF_SPI_DATA1, 0)}, // spi_data1
378-
{P11_4, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_4_SMIF_SPI_DATA2, 0)}, // spi_data2
379-
{P11_3, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_3_SMIF_SPI_DATA3, 0)}, // spi_data3
380-
{P12_0, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_0_SMIF_SPI_DATA4, 0)}, // spi_data4
381-
{P12_1, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_1_SMIF_SPI_DATA5, 0)}, // spi_data5
382-
{P12_2, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_2_SMIF_SPI_DATA6, 0)}, // spi_data6
383-
{P12_3, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_3_SMIF_SPI_DATA7, 0)}, // spi_data7
384-
{NC, NC, 0}
385-
};
386-
387-
// Ensure that the spi_select pins are defined in the order 0 to 3
388-
const PinMap PinMap_QSPI_SSEL[] = { // does not use PERI clock, uses HFCLK2
389-
{P11_2, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_2_SMIF_SPI_SELECT0, 0)}, // spi_select0
390-
{P11_1, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_1_SMIF_SPI_SELECT1, 0)}, // spi_select1
391-
{P11_0, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_0_SMIF_SPI_SELECT2, 0)}, // spi_select2
392-
{P12_4, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_4_SMIF_SPI_SELECT3, 0)}, // spi_select3
393-
{NC, NC, 0}
373+
const PinMap PinMap_QSPI_SSEL[] = {
374+
{P11_2, QSPI_0, CY_GPIO_CFG_CREATE(P11_2_SMIF_SPI_SELECT0, CY_GPIO_DM_STRONG_IN_OFF)},
375+
{NC, NC, 0},
376+
};
377+
const PinMap PinMap_QSPI_DATA0[] = {
378+
{P11_6, QSPI_0, CY_GPIO_CFG_CREATE(P11_6_SMIF_SPI_DATA0, CY_GPIO_DM_STRONG)},
379+
{NC, NC, 0},
380+
};
381+
const PinMap PinMap_QSPI_DATA1[] = {
382+
{P11_5, QSPI_0, CY_GPIO_CFG_CREATE(P11_5_SMIF_SPI_DATA1, CY_GPIO_DM_STRONG)},
383+
{NC, NC, 0},
384+
};
385+
const PinMap PinMap_QSPI_DATA2[] = {
386+
{P11_4, QSPI_0, CY_GPIO_CFG_CREATE(P11_4_SMIF_SPI_DATA2, CY_GPIO_DM_STRONG)},
387+
{NC, NC, 0},
388+
};
389+
const PinMap PinMap_QSPI_DATA3[] = {
390+
{P11_3, QSPI_0, CY_GPIO_CFG_CREATE(P11_3_SMIF_SPI_DATA3, CY_GPIO_DM_STRONG)},
391+
{NC, NC, 0},
394392
};
395393
#endif // DEVICE_QSPI

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/PeripheralNames.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -114,8 +114,8 @@ typedef enum {
114114
} ADCName;
115115

116116
typedef enum {
117-
SMIF_0 = (int)SMIF0_BASE,
118-
} SMIFName;
117+
QSPI_0,
118+
} QSPIName;
119119

120120
#ifdef __cplusplus
121121
}

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/PeripheralPins.c‎

Lines changed: 22 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -464,31 +464,28 @@ const PinMap PinMap_ADC[] = {
464464
#endif // DEVICE_ANALOGIN
465465

466466
#if DEVICE_QSPI
467-
const PinMap PinMap_QSPI_SCLK[] = { // does not use PERI clock, uses HFCLK2
468-
{P11_7, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_7_SMIF_SPI_CLK, 0)},
469-
{NC, NC, 0}
467+
const PinMap PinMap_QSPI_SCLK[] = {
468+
{P11_7, QSPI_0, CY_GPIO_CFG_CREATE(P11_7_SMIF_SPI_CLK, CY_GPIO_DM_STRONG_IN_OFF)},
469+
{NC, NC, 0},
470470
};
471-
472-
// Ensure that the spi_data pins are defined in the order 0 to 7
473-
const PinMap PinMap_QSPI_DATA[] = { // does not use PERI clock, uses HFCLK2
474-
{P11_6, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_6_SMIF_SPI_DATA0, 0)}, // spi_data0
475-
{P11_5, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_5_SMIF_SPI_DATA1, 0)}, // spi_data1
476-
{P11_4, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_4_SMIF_SPI_DATA2, 0)}, // spi_data2
477-
{P11_3, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_3_SMIF_SPI_DATA3, 0)}, // spi_data3
478-
{P12_0, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_0_SMIF_SPI_DATA4, 0)}, // spi_data4
479-
{P12_1, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_1_SMIF_SPI_DATA5, 0)}, // spi_data5
480-
{P12_2, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_2_SMIF_SPI_DATA6, 0)}, // spi_data6
481-
{P12_3, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_3_SMIF_SPI_DATA7, 0)}, // spi_data7
482-
{NC, NC, 0}
483-
};
484-
485-
// Ensure that the spi_select pins are defined in the order 0 to 3
486-
const PinMap PinMap_QSPI_SSEL[] = { // does not use PERI clock, uses HFCLK2
487-
{P11_2, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_2_SMIF_SPI_SELECT0, 0)}, // spi_select0
488-
{P11_1, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_1_SMIF_SPI_SELECT1, 0)}, // spi_select1
489-
{P11_0, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_0_SMIF_SPI_SELECT2, 0)}, // spi_select2
490-
{P12_4, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_4_SMIF_SPI_SELECT3, 0)}, // spi_select3
491-
{NC, NC, 0}
471+
const PinMap PinMap_QSPI_SSEL[] = {
472+
{P11_2, QSPI_0, CY_GPIO_CFG_CREATE(P11_2_SMIF_SPI_SELECT0, CY_GPIO_DM_STRONG_IN_OFF)},
473+
{NC, NC, 0},
474+
};
475+
const PinMap PinMap_QSPI_DATA0[] = {
476+
{P11_6, QSPI_0, CY_GPIO_CFG_CREATE(P11_6_SMIF_SPI_DATA0, CY_GPIO_DM_STRONG)},
477+
{NC, NC, 0},
478+
};
479+
const PinMap PinMap_QSPI_DATA1[] = {
480+
{P11_5, QSPI_0, CY_GPIO_CFG_CREATE(P11_5_SMIF_SPI_DATA1, CY_GPIO_DM_STRONG)},
481+
{NC, NC, 0},
482+
};
483+
const PinMap PinMap_QSPI_DATA2[] = {
484+
{P11_4, QSPI_0, CY_GPIO_CFG_CREATE(P11_4_SMIF_SPI_DATA2, CY_GPIO_DM_STRONG)},
485+
{NC, NC, 0},
486+
};
487+
const PinMap PinMap_QSPI_DATA3[] = {
488+
{P11_3, QSPI_0, CY_GPIO_CFG_CREATE(P11_3_SMIF_SPI_DATA3, CY_GPIO_DM_STRONG)},
489+
{NC, NC, 0},
492490
};
493491
#endif // DEVICE_QSPI
494-

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/PeripheralNames.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -108,8 +108,8 @@ typedef enum {
108108
} DACName;
109109

110110
typedef enum {
111-
SMIF_0 = (int)SMIF0_BASE,
112-
} SMIFName;
111+
QSPI_0,
112+
} QSPIName;
113113

114114
#ifdef __cplusplus
115115
}

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/PeripheralPins.c‎

Lines changed: 22 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -436,30 +436,28 @@ const PinMap PinMap_DAC[] = {
436436
#endif // DEVICE_ANALOGIN
437437

438438
#if DEVICE_QSPI
439-
const PinMap PinMap_QSPI_SCLK[] = { // does not use PERI clock, uses HFCLK2
440-
{P11_7, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_7_SMIF_SPI_CLK, 0)},
441-
{NC, NC, 0}
439+
const PinMap PinMap_QSPI_SCLK[] = {
440+
{P11_7, QSPI_0, CY_GPIO_CFG_CREATE(P11_7_SMIF_SPI_CLK, CY_GPIO_DM_STRONG_IN_OFF)},
441+
{NC, NC, 0},
442442
};
443-
444-
// Ensure that the spi_data pins are defined in the order 0 to 7
445-
const PinMap PinMap_QSPI_DATA[] = { // does not use PERI clock, uses HFCLK2
446-
{P11_6, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_6_SMIF_SPI_DATA0, 0)}, // spi_data0
447-
{P11_5, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_5_SMIF_SPI_DATA1, 0)}, // spi_data1
448-
{P11_4, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_4_SMIF_SPI_DATA2, 0)}, // spi_data2
449-
{P11_3, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_3_SMIF_SPI_DATA3, 0)}, // spi_data3
450-
{P12_0, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_0_SMIF_SPI_DATA4, 0)}, // spi_data4
451-
{P12_1, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_1_SMIF_SPI_DATA5, 0)}, // spi_data5
452-
{P12_2, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_2_SMIF_SPI_DATA6, 0)}, // spi_data6
453-
{P12_3, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_3_SMIF_SPI_DATA7, 0)}, // spi_data7
454-
{NC, NC, 0}
455-
};
456-
457-
// Ensure that the spi_select pins are defined in the order 0 to 3
458-
const PinMap PinMap_QSPI_SSEL[] = { // does not use PERI clock, uses HFCLK2
459-
{P11_2, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_2_SMIF_SPI_SELECT0, 0)}, // spi_select0
460-
{P11_1, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_1_SMIF_SPI_SELECT1, 0)}, // spi_select1
461-
{P11_0, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_0_SMIF_SPI_SELECT2, 0)}, // spi_select2
462-
{P12_4, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_4_SMIF_SPI_SELECT3, 0)}, // spi_select3
463-
{NC, NC, 0}
443+
const PinMap PinMap_QSPI_SSEL[] = {
444+
{P11_2, QSPI_0, CY_GPIO_CFG_CREATE(P11_2_SMIF_SPI_SELECT0, CY_GPIO_DM_STRONG_IN_OFF)},
445+
{NC, NC, 0},
446+
};
447+
const PinMap PinMap_QSPI_DATA0[] = {
448+
{P11_6, QSPI_0, CY_GPIO_CFG_CREATE(P11_6_SMIF_SPI_DATA0, CY_GPIO_DM_STRONG)},
449+
{NC, NC, 0},
450+
};
451+
const PinMap PinMap_QSPI_DATA1[] = {
452+
{P11_5, QSPI_0, CY_GPIO_CFG_CREATE(P11_5_SMIF_SPI_DATA1, CY_GPIO_DM_STRONG)},
453+
{NC, NC, 0},
454+
};
455+
const PinMap PinMap_QSPI_DATA2[] = {
456+
{P11_4, QSPI_0, CY_GPIO_CFG_CREATE(P11_4_SMIF_SPI_DATA2, CY_GPIO_DM_STRONG)},
457+
{NC, NC, 0},
458+
};
459+
const PinMap PinMap_QSPI_DATA3[] = {
460+
{P11_3, QSPI_0, CY_GPIO_CFG_CREATE(P11_3_SMIF_SPI_DATA3, CY_GPIO_DM_STRONG)},
461+
{NC, NC, 0},
464462
};
465463
#endif // DEVICE_QSPI

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