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lines changed Original file line number Diff line number Diff line change @@ -88,7 +88,7 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
8888 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0 };
8989 RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInitStruct = { 0 };
9090
91- #if HSE_VALUE > 48000000 || HSE_VALUE < 4000000
91+ #if HSE_VALUE != 4000000 && HSE_VALUE != 8000000 && HSE_VALUE != 16000000 && HSE_VALUE != 24000000
9292#error Unsupported externall clock value, check HSE_VALUE define
9393#endif
9494
@@ -100,7 +100,16 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
100100 RCC_OscInitStruct .HSEState = RCC_HSE_ON ;
101101 RCC_OscInitStruct .PLL .PLLState = RCC_PLL_ON ;
102102 RCC_OscInitStruct .PLL .PLLSource = RCC_PLLSOURCE_HSE ;
103+ #if HSE_VALUE == 4000000
104+ RCC_OscInitStruct .PLL .PLLM = RCC_PLLM_DIV1 ;
105+ #elif HSE_VALUE == 8000000
106+ RCC_OscInitStruct .PLL .PLLM = RCC_PLLM_DIV2 ;
107+ #elif HSE_VALUE == 16000000
108+ RCC_OscInitStruct .PLL .PLLM = RCC_PLLM_DIV4 ;
109+ #elif HSE_VALUE == 24000000
103110 RCC_OscInitStruct .PLL .PLLM = RCC_PLLM_DIV6 ;
111+ #endif
112+
104113 //! 170MHz as a core frequency for FDCAN is not suitable for many frequencies,
105114 //! as it provides low accuracy. When no FDCAN is used, the full capacity of 170 MHz
106115 //! should be standard.
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