MIMXRT1050: Update the drivers to SDK 2.6

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>

Author: mmahadevan108

targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_adc.c

@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_adc.h"
@@ -39,7 +13,6 @@
 #define FSL_COMPONENT_ID "platform.drivers.adc_12b1msps_sar"
 #endif
 
-
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/
@@ -56,8 +29,10 @@ static uint32_t ADC_GetInstance(ADC_Type *base);
 /*! @brief Pointers to ADC bases for each instance. */
 static ADC_Type *const s_adcBases[] = ADC_BASE_PTRS;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /*! @brief Pointers to ADC clocks for each instance. */
 static const clock_ip_name_t s_adcClocks[] = ADC_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /*******************************************************************************
  * Code
@@ -80,14 +55,22 @@ static uint32_t ADC_GetInstance(ADC_Type *base)
     return instance;
 }
 
+/*!
+ * brief Initialize the ADC module.
+ *
+ * param base ADC peripheral base address.
+ * param config Pointer to "adc_config_t" structure.
+ */
 void ADC_Init(ADC_Type *base, const adc_config_t *config)
 {
     assert(NULL != config);
 
     uint32_t tmp32;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Enable the clock. */
     CLOCK_EnableClock(s_adcClocks[ADC_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
     /* ADCx_CFG */
     tmp32 = base->CFG & (ADC_CFG_AVGS_MASK | ADC_CFG_ADTRG_MASK); /* Reserve AVGS and ADTRG bits. */
     tmp32 |= ADC_CFG_REFSEL(config->referenceVoltageSource) | ADC_CFG_ADSTS(config->samplePeriodMode) |
@@ -123,33 +106,90 @@ void ADC_Init(ADC_Type *base, const adc_config_t *config)
     base->GC = tmp32;
 }
 
+/*!
+ * brief De-initializes the ADC module.
+ *
+ * param base ADC peripheral base address.
+ */
 void ADC_Deinit(ADC_Type *base)
 {
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Disable the clock. */
     CLOCK_DisableClock(s_adcClocks[ADC_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
+/*!
+ * brief Gets an available pre-defined settings for the converter's configuration.
+ *
+ * This function initializes the converter configuration structure with available settings. The default values are:
+ * code
+ *  config->enableAsynchronousClockOutput = true;
+ *  config->enableOverWrite =               false;
+ *  config->enableContinuousConversion =    false;
+ *  config->enableHighSpeed =               false;
+ *  config->enableLowPower =                false;
+ *  config->enableLongSample =              false;
+ *  config->referenceVoltageSource =        kADC_ReferenceVoltageSourceAlt0;
+ *  config->samplePeriodMode =              kADC_SamplePeriod2or12Clocks;
+ *  config->clockSource =                   kADC_ClockSourceAD;
+ *  config->clockDriver =                   kADC_ClockDriver1;
+ *  config->resolution =                    kADC_Resolution12Bit;
+ * endcode
+ * param base   ADC peripheral base address.
+ * param config Pointer to the configuration structure.
+ */
 void ADC_GetDefaultConfig(adc_config_t *config)
 {
     assert(NULL != config);
 
+    /* Initializes the configure structure to zero. */
+    memset(config, 0, sizeof(*config));
+
     config->enableAsynchronousClockOutput = true;
-    config->enableOverWrite = false;
-    config->enableContinuousConversion = false;
-    config->enableHighSpeed = false;
-    config->enableLowPower = false;
-    config->enableLongSample = false;
-    config->referenceVoltageSource = kADC_ReferenceVoltageSourceAlt0;
-    config->samplePeriodMode = kADC_SamplePeriod2or12Clocks;
-    config->clockSource = kADC_ClockSourceAD;
-    config->clockDriver = kADC_ClockDriver1;
-    config->resolution = kADC_Resolution12Bit;
+    config->enableOverWrite               = false;
+    config->enableContinuousConversion    = false;
+    config->enableHighSpeed               = false;
+    config->enableLowPower                = false;
+    config->enableLongSample              = false;
+    config->referenceVoltageSource        = kADC_ReferenceVoltageSourceAlt0;
+    config->samplePeriodMode              = kADC_SamplePeriod2or12Clocks;
+    config->clockSource                   = kADC_ClockSourceAD;
+    config->clockDriver                   = kADC_ClockDriver1;
+    config->resolution                    = kADC_Resolution12Bit;
 }
 
+/*!
+ * brief Configures the conversion channel.
+ *
+ * This operation triggers the conversion when in software trigger mode. When in hardware trigger mode, this API
+ * configures the channel while the external trigger source helps to trigger the conversion.
+ *
+ * Note that the "Channel Group" has a detailed description.
+ * To allow sequential conversions of the ADC to be triggered by internal peripherals, the ADC has more than one
+ * group of status and control registers, one for each conversion. The channel group parameter indicates which group of
+ * registers are used, for example channel group 0 is for Group A registers and channel group 1 is for Group B
+ * registers. The
+ * channel groups are used in a "ping-pong" approach to control the ADC operation.  At any point, only one of
+ * the channel groups is actively controlling ADC conversions. The channel group 0 is used for both software and
+ * hardware
+ * trigger modes. Channel groups 1 and greater indicate potentially multiple channel group registers for
+ * use only in hardware trigger mode. See the chip configuration information in the appropriate MCU reference manual
+ * about the
+ * number of SC1n registers (channel groups) specific to this device.  None of the channel groups 1 or greater are used
+ * for software trigger operation. Therefore, writing to these channel groups does not initiate a new conversion.
+ * Updating the channel group 0 while a different channel group is actively controlling a conversion is allowed and
+ * vice versa. Writing any of the channel group registers while that specific channel group is actively controlling a
+ * conversion aborts the current conversion.
+ *
+ * param base          ADC peripheral base address.
+ * param channelGroup  Channel group index.
+ * param config        Pointer to the "adc_channel_config_t" structure for the conversion channel.
+ */
 void ADC_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc_channel_config_t *config)
 {
     assert(NULL != config);
-    assert(channelGroup < ADC_HC_COUNT);
+    assert(channelGroup < FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT);
 
     uint32_t tmp32;
 
@@ -168,6 +208,19 @@ void ADC_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc_chann
  *  3. Check the status of CALF bit in ADC_GS and the CAL bit in ADC_GC.
  *  4. When CAL bit becomes '0' then check the CALF status and COCO[0] bit status.
  */
+/*!
+ * brief  Automates the hardware calibration.
+ *
+ * This auto calibration helps to adjust the plus/minus side gain automatically.
+ * Execute the calibration before using the converter. Note that the software trigger should be used
+ * during calibration.
+ *
+ * param  base ADC peripheral base address.
+ *
+ * return                 Execution status.
+ * retval kStatus_Success Calibration is done successfully.
+ * retval kStatus_Fail    Calibration has failed.
+ */
 status_t ADC_DoAutoCalibration(ADC_Type *base)
 {
     status_t status = kStatus_Success;
@@ -222,6 +275,12 @@ status_t ADC_DoAutoCalibration(ADC_Type *base)
     return status;
 }
 
+/*!
+ * brief Set user defined offset.
+ *
+ * param base   ADC peripheral base address.
+ * param config Pointer to "adc_offest_config_t" structure.
+ */
 void ADC_SetOffsetConfig(ADC_Type *base, const adc_offest_config_t *config)
 {
     assert(NULL != config);
@@ -236,6 +295,19 @@ void ADC_SetOffsetConfig(ADC_Type *base, const adc_offest_config_t *config)
     base->OFS = tmp32;
 }
 
+/*!
+ * brief Configures the hardware compare mode.
+ *
+ * The hardware compare mode provides a way to process the conversion result automatically by using hardware. Only the
+ * result
+ * in the compare range is available. To compare the range, see "adc_hardware_compare_mode_t" or the appopriate
+ * reference
+ * manual for more information.
+ *
+ * param base ADC peripheral base address.
+ * param Pointer to "adc_hardware_compare_config_t" structure.
+ *
+ */
 void ADC_SetHardwareCompareConfig(ADC_Type *base, const adc_hardware_compare_config_t *config)
 {
     uint32_t tmp32;
@@ -269,10 +341,20 @@ void ADC_SetHardwareCompareConfig(ADC_Type *base, const adc_hardware_compare_con
     base->GC = tmp32;
 
     /* Load the compare values. */
-    tmp32 = ADC_CV_CV1(config->value1) | ADC_CV_CV2(config->value2);
+    tmp32    = ADC_CV_CV1(config->value1) | ADC_CV_CV2(config->value2);
     base->CV = tmp32;
 }
 
+/*!
+ * brief Configures the hardware average mode.
+ *
+ * The hardware average mode provides a way to process the conversion result automatically by using hardware. The
+ * multiple
+ * conversion results are accumulated and averaged internally making them easier to read.
+ *
+ * param base ADC peripheral base address.
+ * param mode Setting the hardware average mode. See "adc_hardware_average_mode_t".
+ */
 void ADC_SetHardwareAverageConfig(ADC_Type *base, adc_hardware_average_mode_t mode)
 {
     uint32_t tmp32;
@@ -290,6 +372,12 @@ void ADC_SetHardwareAverageConfig(ADC_Type *base, adc_hardware_average_mode_t mo
     }
 }
 
+/*!
+ * brief Clears the converter's status falgs.
+ *
+ * param base ADC peripheral base address.
+ * param mask Mask value for the cleared flags. See "adc_status_flags_t".
+ */
 void ADC_ClearStatusFlags(ADC_Type *base, uint32_t mask)
 {
     uint32_t tmp32 = 0;

targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_adc.h

@@ -1,35 +1,9 @@
 /*
- * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #ifndef _FSL_ADC_H_
@@ -43,20 +17,20 @@
  */
 
 /*******************************************************************************
-* Definitions
-******************************************************************************/
+ * Definitions
+ ******************************************************************************/
 /*! @brief ADC driver version */
-#define FSL_ADC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
+#define FSL_ADC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*!< Version 2.0.2. */
 
 /*!
  * @brief Converter's status flags.
  */
 typedef enum _adc_status_flags
 {
-    kADC_ConversionActiveFlag = ADC_GS_ADACT_MASK, /*!< Conversion is active,not support w1c. */
-    kADC_CalibrationFailedFlag = ADC_GS_CALF_MASK, /*!< Calibration is failed,support w1c. */
+    kADC_ConversionActiveFlag  = ADC_GS_ADACT_MASK, /*!< Conversion is active,not support w1c. */
+    kADC_CalibrationFailedFlag = ADC_GS_CALF_MASK,  /*!< Calibration is failed,support w1c. */
     kADC_AsynchronousWakeupInterruptFlag =
-        ADC_GS_AWKST_MASK, /*!< Asynchronous wakeup interrupt occured, support w1c. */
+        ADC_GS_AWKST_MASK, /*!< Asynchronous wakeup interrupt occurred, support w1c. */
 } adc_status_flags_t;
 
 /*!
@@ -95,7 +69,7 @@ typedef enum _adc_sample_period_mode
  */
 typedef enum _adc_clock_source
 {
-    kADC_ClockSourceIPG = 0U,     /*!< Select IPG clock to generate ADCK. */
+    kADC_ClockSourceIPG     = 0U, /*!< Select IPG clock to generate ADCK. */
     kADC_ClockSourceIPGDiv2 = 1U, /*!< Select IPG clock divided by 2 to generate ADCK. */
 #if !(defined(FSL_FEATURE_ADC_SUPPORT_ALTCLK_REMOVE) && FSL_FEATURE_ADC_SUPPORT_ALTCLK_REMOVE)
     kADC_ClockSourceALT = 2U, /*!< Select alternate clock to generate ADCK. */
@@ -119,7 +93,7 @@ typedef enum _adc_clock_drvier
  */
 typedef enum _adc_resolution
 {
-    kADC_Resolution8Bit = 0U,  /*!< Single End 8-bit resolution. */
+    kADC_Resolution8Bit  = 0U, /*!< Single End 8-bit resolution. */
     kADC_Resolution10Bit = 1U, /*!< Single End 10-bit resolution. */
     kADC_Resolution12Bit = 2U, /*!< Single End 12-bit resolution. */
 } adc_resolution_t;
@@ -146,10 +120,10 @@ typedef enum _adc_hardware_compare_mode
  */
 typedef enum _adc_hardware_average_mode
 {
-    kADC_HardwareAverageCount4 = 0U,   /*!< For hardware average with 4 samples. */
-    kADC_HardwareAverageCount8 = 1U,   /*!< For hardware average with 8 samples. */
-    kADC_HardwareAverageCount16 = 2U,  /*!< For hardware average with 16 samples. */
-    kADC_HardwareAverageCount32 = 3U,  /*!< For hardware average with 32 samples. */
+    kADC_HardwareAverageCount4   = 0U, /*!< For hardware average with 4 samples. */
+    kADC_HardwareAverageCount8   = 1U, /*!< For hardware average with 8 samples. */
+    kADC_HardwareAverageCount16  = 2U, /*!< For hardware average with 16 samples. */
+    kADC_HardwareAverageCount32  = 3U, /*!< For hardware average with 32 samples. */
     kADC_HardwareAverageDiasable = 4U, /*!< Disable the hardware average function. */
 } adc_hardware_average_mode_t;
 
@@ -214,8 +188,8 @@ typedef struct _adc_channel_config
     bool enableInterruptOnConversionCompleted; /*!< Generate an interrupt request once the conversion is completed. */
 } adc_channel_config_t;
 /*******************************************************************************
-* API
-******************************************************************************/
+ * API
+ ******************************************************************************/
 #if defined(__cplusplus)
 extern "C" {
 #endif
@@ -301,7 +275,7 @@ void ADC_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc_chann
  */
 static inline uint32_t ADC_GetChannelConversionValue(ADC_Type *base, uint32_t channelGroup)
 {
-    assert(channelGroup < ADC_R_COUNT);
+    assert(channelGroup < FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT);
 
     return base->R[channelGroup];
 }
@@ -325,7 +299,7 @@ static inline uint32_t ADC_GetChannelConversionValue(ADC_Type *base, uint32_t ch
  */
 static inline uint32_t ADC_GetChannelStatusFlags(ADC_Type *base, uint32_t channelGroup)
 {
-    assert(channelGroup < ADC_HC_COUNT);
+    assert(channelGroup < FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT);
 
     /* If flag is set,return 1,otherwise, return 0. */
     return (((base->HS) & (1U << channelGroup)) >> channelGroup);