Merge pull request #12583 from jeromecoutant/PR_BAREMETAL

STM32F7: baremetal profile support

Author: 0xc0170

targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_DISCO_F746NG/system_clock.c

@@ -150,6 +150,11 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
     __PWR_CLK_ENABLE();
     __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
 
+    // Select HSI as system clock source to allow modification of the PLL configuration
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
+    HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
+
     // Enable HSE oscillator and activate PLL with HSE as source
     RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
     if (bypass == 0) {
@@ -208,6 +213,11 @@ uint8_t SetSysClock_PLL_HSI(void)
     // Enable power clock
     __PWR_CLK_ENABLE();
 
+    // Select HSI as system clock source to allow modification of the PLL configuration
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
+    HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
+
     // Enable HSI oscillator and activate PLL with HSI as source
     RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI;
     RCC_OscInitStruct.HSIState            = RCC_HSI_ON;

targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/system_clock.c

@@ -150,6 +150,11 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
     __PWR_CLK_ENABLE();
     __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
 
+    // Select HSI as system clock source to allow modification of the PLL configuration
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
+    HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
+
     // Enable HSE oscillator and activate PLL with HSE as source
     RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
     if (bypass == 0) {
@@ -208,6 +213,11 @@ uint8_t SetSysClock_PLL_HSI(void)
     // Enable power clock
     __PWR_CLK_ENABLE();
 
+    // Select HSI as system clock source to allow modification of the PLL configuration
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
+    HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
+
     // Enable HSI oscillator and activate PLL with HSI as source
     RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI;
     RCC_OscInitStruct.HSIState            = RCC_HSI_ON;

targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/TOOLCHAIN_ARM_STD/stm32f746xg.sct

@@ -68,6 +68,9 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE  {    ; load region size_region
    .ANY (+RW +ZI)
   }
 
+  ARM_LIB_HEAP  AlignExpr(+0, 16)  EMPTY  (MBED_RAM0_START + MBED_RAM0_SIZE - Stack_Size - AlignExpr(ImageLimit(RW_IRAM1), 16))  { ; Heap growing up
+  }
+
   ARM_LIB_STACK (MBED_RAM0_START+MBED_RAM0_SIZE) EMPTY -Stack_Size { ; stack
   }
 }

targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/system_clock.c

@@ -150,6 +150,11 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
     __PWR_CLK_ENABLE();
     __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
 
+    // Select HSI as system clock source to allow modification of the PLL configuration
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
+    HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
+
     // Enable HSE oscillator and activate PLL with HSE as source
     RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
     if (bypass == 0) {
@@ -208,6 +213,11 @@ uint8_t SetSysClock_PLL_HSI(void)
     // Enable power clock
     __PWR_CLK_ENABLE();
 
+    // Select HSI as system clock source to allow modification of the PLL configuration
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
+    HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
+
     // Enable HSI oscillator and activate PLL with HSI as source
     RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI;
     RCC_OscInitStruct.HSIState            = RCC_HSI_ON;

targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/TOOLCHAIN_ARM_STD/stm32f756xg.sct

@@ -68,6 +68,9 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE  {    ; load region size_region
    .ANY (+RW +ZI)
   }
 
+  ARM_LIB_HEAP  AlignExpr(+0, 16)  EMPTY  (MBED_RAM0_START + MBED_RAM0_SIZE - Stack_Size - AlignExpr(ImageLimit(RW_IRAM1), 16))  { ; Heap growing up
+  }
+
   ARM_LIB_STACK (MBED_RAM0_START+MBED_RAM0_SIZE) EMPTY -Stack_Size { ; stack
   }
 }

targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/system_clock.c

@@ -150,6 +150,11 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
     __PWR_CLK_ENABLE();
     __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
 
+    // Select HSI as system clock source to allow modification of the PLL configuration
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
+    HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
+
     // Enable HSE oscillator and activate PLL with HSE as source
     RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
     if (bypass == 0) {
@@ -209,6 +214,11 @@ uint8_t SetSysClock_PLL_HSI(void)
     // Enable power clock
     __PWR_CLK_ENABLE();
 
+    // Select HSI as system clock source to allow modification of the PLL configuration
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
+    HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
+
     // Enable HSI oscillator and activate PLL with HSI as source
     RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI;
     RCC_OscInitStruct.HSIState            = RCC_HSI_ON;

targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_ARM_STD/stm32f767xi.sct

@@ -68,6 +68,9 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE  {    ; load region size_region
    .ANY (+RW +ZI)
   }
 
+  ARM_LIB_HEAP  AlignExpr(+0, 16)  EMPTY  (MBED_RAM0_START + MBED_RAM0_SIZE - Stack_Size - AlignExpr(ImageLimit(RW_IRAM1), 16))  { ; Heap growing up
+  }
+
   ARM_LIB_STACK (MBED_RAM0_START+MBED_RAM0_SIZE) EMPTY -Stack_Size { ; stack
   }
 }

targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/system_clock.c

@@ -150,6 +150,11 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
     __PWR_CLK_ENABLE();
     __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
 
+    // Select HSI as system clock source to allow modification of the PLL configuration
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
+    HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
+
     // Enable HSE oscillator and activate PLL with HSE as source
     RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
     if (bypass == 0) {
@@ -212,6 +217,11 @@ uint8_t SetSysClock_PLL_HSI(void)
     // Enable power clock
     __PWR_CLK_ENABLE();
 
+    // Select HSI as system clock source to allow modification of the PLL configuration
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
+    HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
+
     // Enable HSI oscillator and activate PLL with HSI as source
     RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI;
     RCC_OscInitStruct.HSIState            = RCC_HSI_ON;

targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/device/TOOLCHAIN_ARM_STD/stm32f769xi.sct

@@ -68,6 +68,9 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE  {    ; load region size_region
    .ANY (+RW +ZI)
   }
 
+  ARM_LIB_HEAP  AlignExpr(+0, 16)  EMPTY  (MBED_RAM0_START + MBED_RAM0_SIZE - Stack_Size - AlignExpr(ImageLimit(RW_IRAM1), 16))  { ; Heap growing up
+  }
+
   ARM_LIB_STACK (MBED_RAM0_START+MBED_RAM0_SIZE) EMPTY -Stack_Size { ; stack
   }
 }