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Merge pull request #14348 from harmut01/baremetal_arm_fm
Add bare metal support to ARM FM targets
2 parents 876032b + 3c57f38 commit 87ceded

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6 files changed

+102
-57
lines changed
  • targets
    • TARGET_ARM_FM/TARGET_FVP_MPS2
      • TARGET_FVP_MPS2_M0P/device/TOOLCHAIN_ARM_STD
      • TARGET_FVP_MPS2_M0/device/TOOLCHAIN_ARM_STD
      • TARGET_FVP_MPS2_M3/device/TOOLCHAIN_ARM_STD
      • TARGET_FVP_MPS2_M4/device/TOOLCHAIN_ARM_STD
      • TARGET_FVP_MPS2_M7/device/TOOLCHAIN_ARM_STD
    • targets.json

6 files changed

+102
-57
lines changed

‎targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/TOOLCHAIN_ARM_STD/MPS2.sct‎

Lines changed: 18 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -52,17 +52,24 @@
5252
#define STACK_SIZE MBED_CONF_TARGET_BOOT_STACK_SIZE
5353
#endif
5454

55+
#define ZBT_SRAM2_RAM_FIXED_SIZE (MBED_CONF_TARGET_BOOT_STACK_SIZE + NVIC_VECTORS_SIZE)
56+
5557
; The vector table is loaded at address 0x00000000 in Flash memory region.
5658
LR_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load region size_region
57-
ER_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load address = execution address
58-
*.o (RESET, +First)
59-
*(InRoot$$Sections)
60-
*(+RO)
61-
}
62-
; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
63-
RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE - STACK_SIZE) { ; RW data
64-
*(+RW +ZI)
65-
}
66-
ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down
67-
}
59+
ER_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load address = execution address
60+
*.o (RESET, +First)
61+
*(InRoot$$Sections)
62+
*(+RO)
63+
}
64+
65+
; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
66+
RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE - STACK_SIZE) { ; RW data
67+
*(+RW +ZI)
68+
}
69+
70+
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (ZBT_SRAM2_SIZE - ZBT_SRAM2_RAM_FIXED_SIZE - (AlignExpr(ImageLimit(RW_IRAM1), 16) - ZBT_SRAM2_START)) { ; Heap growing upward
71+
}
72+
73+
ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down
74+
}
6875
}

‎targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/TOOLCHAIN_ARM_STD/MPS2.sct‎

Lines changed: 18 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -52,17 +52,24 @@
5252
#define STACK_SIZE MBED_CONF_TARGET_BOOT_STACK_SIZE
5353
#endif
5454

55+
#define ZBT_SRAM2_RAM_FIXED_SIZE (MBED_CONF_TARGET_BOOT_STACK_SIZE + NVIC_VECTORS_SIZE)
56+
5557
; The vector table is loaded at address 0x00000000 in Flash memory region.
5658
LR_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load region size_region
57-
ER_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load address = execution address
58-
*.o (RESET, +First)
59-
*(InRoot$$Sections)
60-
*(+RO)
61-
}
62-
; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
63-
RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE - STACK_SIZE) { ; RW data
64-
*(+RW +ZI)
65-
}
66-
ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down
67-
}
59+
ER_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load address = execution address
60+
*.o (RESET, +First)
61+
*(InRoot$$Sections)
62+
*(+RO)
63+
}
64+
65+
; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
66+
RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE - STACK_SIZE) { ; RW data
67+
*(+RW +ZI)
68+
}
69+
70+
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (ZBT_SRAM2_SIZE - ZBT_SRAM2_RAM_FIXED_SIZE - (AlignExpr(ImageLimit(RW_IRAM1), 16) - ZBT_SRAM2_START)) { ; Heap growing upward
71+
}
72+
73+
ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down
74+
}
6875
}

‎targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/TOOLCHAIN_ARM_STD/MPS2.sct‎

Lines changed: 18 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -52,17 +52,24 @@
5252
#define STACK_SIZE MBED_CONF_TARGET_BOOT_STACK_SIZE
5353
#endif
5454

55+
#define ZBT_SRAM2_RAM_FIXED_SIZE (MBED_CONF_TARGET_BOOT_STACK_SIZE + NVIC_VECTORS_SIZE)
56+
5557
; The vector table is loaded at address 0x00000000 in Flash memory region.
5658
LR_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load region size_region
57-
ER_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load address = execution address
58-
*.o (RESET, +First)
59-
*(InRoot$$Sections)
60-
*(+RO)
61-
}
62-
; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
63-
RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE - STACK_SIZE) { ; RW data
64-
*(+RW +ZI)
65-
}
66-
ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down
67-
}
59+
ER_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load address = execution address
60+
*.o (RESET, +First)
61+
*(InRoot$$Sections)
62+
*(+RO)
63+
}
64+
65+
; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
66+
RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE - STACK_SIZE) { ; RW data
67+
*(+RW +ZI)
68+
}
69+
70+
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (ZBT_SRAM2_SIZE - ZBT_SRAM2_RAM_FIXED_SIZE - (AlignExpr(ImageLimit(RW_IRAM1), 16) - ZBT_SRAM2_START)) { ; Heap growing upward
71+
}
72+
73+
ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down
74+
}
6875
}

‎targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/TOOLCHAIN_ARM_STD/MPS2.sct‎

Lines changed: 18 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -52,17 +52,24 @@
5252
#define STACK_SIZE MBED_CONF_TARGET_BOOT_STACK_SIZE
5353
#endif
5454

55+
#define ZBT_SRAM2_RAM_FIXED_SIZE (MBED_CONF_TARGET_BOOT_STACK_SIZE + NVIC_VECTORS_SIZE)
56+
5557
; The vector table is loaded at address 0x00000000 in Flash memory region.
5658
LR_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load region size_region
57-
ER_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load address = execution address
58-
*.o (RESET, +First)
59-
*(InRoot$$Sections)
60-
*(+RO)
61-
}
62-
; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
63-
RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE - STACK_SIZE) { ; RW data
64-
*(+RW +ZI)
65-
}
66-
ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down
67-
}
59+
ER_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load address = execution address
60+
*.o (RESET, +First)
61+
*(InRoot$$Sections)
62+
*(+RO)
63+
}
64+
65+
; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
66+
RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE - STACK_SIZE) { ; RW data
67+
*(+RW +ZI)
68+
}
69+
70+
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (ZBT_SRAM2_SIZE - ZBT_SRAM2_RAM_FIXED_SIZE - (AlignExpr(ImageLimit(RW_IRAM1), 16) - ZBT_SRAM2_START)) { ; Heap growing upward
71+
}
72+
73+
ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down
74+
}
6875
}

‎targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/TOOLCHAIN_ARM_STD/MPS2.sct‎

Lines changed: 18 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -52,17 +52,24 @@
5252
#define STACK_SIZE MBED_CONF_TARGET_BOOT_STACK_SIZE
5353
#endif
5454

55+
#define ZBT_SRAM2_RAM_FIXED_SIZE (MBED_CONF_TARGET_BOOT_STACK_SIZE + NVIC_VECTORS_SIZE)
56+
5557
; The vector table is loaded at address 0x00000000 in Flash memory region.
5658
LR_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load region size_region
57-
ER_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load address = execution address
58-
*.o (RESET, +First)
59-
*(InRoot$$Sections)
60-
*(+RO)
61-
}
62-
; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
63-
RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE - STACK_SIZE) { ; RW data
64-
*(+RW +ZI)
65-
}
66-
ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down
67-
}
59+
ER_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load address = execution address
60+
*.o (RESET, +First)
61+
*(InRoot$$Sections)
62+
*(+RO)
63+
}
64+
65+
; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
66+
RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE - STACK_SIZE) { ; RW data
67+
*(+RW +ZI)
68+
}
69+
70+
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (ZBT_SRAM2_SIZE - ZBT_SRAM2_RAM_FIXED_SIZE - (AlignExpr(ImageLimit(RW_IRAM1), 16) - ZBT_SRAM2_START)) { ; Heap growing upward
71+
}
72+
73+
ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down
74+
}
6875
}

‎targets/targets.json‎

Lines changed: 12 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6545,8 +6545,7 @@
65456545
"public": false,
65466546
"supported_toolchains": [
65476547
"GCC_ARM",
6548-
"ARM",
6549-
"IAR"
6548+
"ARM"
65506549
],
65516550
"OUTPUT_EXT": "elf",
65526551
"device_has": [
@@ -6578,6 +6577,17 @@
65786577
],
65796578
"overrides": {
65806579
"network-default-interface-type": "ETHERNET"
6580+
},
6581+
"supported_application_profiles" : ["full", "bare-metal"],
6582+
"supported_c_libs": {
6583+
"arm": [
6584+
"std",
6585+
"small"
6586+
],
6587+
"gcc_arm": [
6588+
"std",
6589+
"small"
6590+
]
65816591
}
65826592
},
65836593
"FVP_MPS2_M0": {

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