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lines changed Original file line number Diff line number Diff line change 20522052 " LPC"
20532053 ],
20542054 "detect_code" : [" 0236" ],
2055+ "device_name" : " LPC55S69JBD100" ,
20552056 "release_versions" : [" 5" ]
20562057 },
20572058 "LPC55S69_NS" : {
Original file line number Diff line number Diff line change @@ -157016,6 +157016,110 @@
157016157016 ],
157017157017 "vendor": "NXP:11"
157018157018 },
157019+ "LPC55S69JBD100": {
157020+ "algorithms": [
157021+ {
157022+ "default": false,
157023+ "file_name": "arm/LPC55XX_640.FLM",
157024+ "ram_size": 4096,
157025+ "ram_start": 536870912,
157026+ "size": 622592,
157027+ "start": 0
157028+ }
157029+ ],
157030+ "from_pack": {
157031+ "pack": "LPC55S69_DFP",
157032+ "url": "http://mcuxpresso.nxp.com/cmsis_pack/repo/",
157033+ "vendor": "NXP",
157034+ "version": "11.0.0"
157035+ },
157036+ "memories": {
157037+ "PROGRAM_FLASH": {
157038+ "access": {
157039+ "execute": true,
157040+ "non_secure": false,
157041+ "non_secure_callable": false,
157042+ "peripheral": false,
157043+ "read": true,
157044+ "secure": false,
157045+ "write": false
157046+ },
157047+ "default": true,
157048+ "size": 622592,
157049+ "start": 0,
157050+ "startup": true
157051+ },
157052+ "SRAMX": {
157053+ "access": {
157054+ "execute": false,
157055+ "non_secure": false,
157056+ "non_secure_callable": false,
157057+ "peripheral": false,
157058+ "read": true,
157059+ "secure": false,
157060+ "write": true
157061+ },
157062+ "default": false,
157063+ "size": 32768,
157064+ "start": 67108864,
157065+ "startup": false
157066+ },
157067+ "SRAM": {
157068+ "access": {
157069+ "execute": false,
157070+ "non_secure": false,
157071+ "non_secure_callable": false,
157072+ "peripheral": false,
157073+ "read": true,
157074+ "secure": false,
157075+ "write": true
157076+ },
157077+ "default": true,
157078+ "size": 278528,
157079+ "start": 536870912,
157080+ "startup": false
157081+ },
157082+ "USB_RAM": {
157083+ "access": {
157084+ "execute": false,
157085+ "non_secure": false,
157086+ "non_secure_callable": false,
157087+ "peripheral": false,
157088+ "read": true,
157089+ "secure": false,
157090+ "write": true
157091+ },
157092+ "default": false,
157093+ "size": 16384,
157094+ "start": 1074790400,
157095+ "startup": false
157096+ }
157097+ },
157098+ "name": "LPC55S69JBD100",
157099+ "processor": {
157100+ "Asymmetric": {
157101+ "cm33_core0": {
157102+ "core": "CortexM33",
157103+ "fpu": "SinglePrecision",
157104+ "mpu": "Present",
157105+ "units": 1
157106+ },
157107+ "cm33_core1": {
157108+ "core": "CortexM33",
157109+ "fpu": "None",
157110+ "mpu": "NotPresent",
157111+ "units": 1
157112+ }
157113+ }
157114+ },
157115+ "sectors": [
157116+ [
157117+ 0,
157118+ 32768
157119+ ]
157120+ ],
157121+ "vendor": "NXP:11"
157122+ },
157019157123 "LPC802M001JDH16": {
157020157124 "algorithms": [
157021157125 {
Original file line number Diff line number Diff line change 9696 "LPC54628J512ET180" : {
9797 "OGChipSelectEditMenu" : " LPC54618J512\t NXP LPC54618J512"
9898 },
99+ "LPC55S69JBD100" : {
100+ "OGChipSelectEditMenu" : " LPC55S69_core0\t NXP LPC55S69_core0"
101+ },
99102 "STM32F072RB" : {
100103 "OGChipSelectEditMenu" : " STM32F072RB\t ST STM32F072RB"
101104 },
Original file line number Diff line number Diff line change @@ -137,7 +137,8 @@ class Uvision(Exporter):
137137 "LPC4088Code.binary_hook" ,
138138 "MTSCode.combine_bins_mts_dot" ,
139139 "MTSCode.combine_bins_mts_dragonfly" ,
140- "NCS36510TargetCode.ncs36510_addfib"
140+ "NCS36510TargetCode.ncs36510_addfib" ,
141+ "LPC55S69Code.binary_hook"
141142 ])
142143
143144 # File associations within .uvprojx file
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