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TARGET_STM/TARGET_STM32WL
TARGET_STM32WL55xC/TARGET_NUCLEO_WL55JC Expand file tree Collapse file tree 7 files changed +179
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lines changed Original file line number Diff line number Diff line change @@ -16,6 +16,7 @@ target_sources(mbed-stm32wl
1616 pwmout_device.c
1717 serial_device.c
1818 spi_api.c
19+ system_clock.c
1920)
2021
2122target_include_directories (mbed-stm32wl
File renamed without changes.
Original file line number Diff line number Diff line change @@ -6,7 +6,6 @@ add_library(mbed-nucleo-wl55jc INTERFACE)
66target_sources (mbed-nucleo-wl55jc
77 INTERFACE
88 PeripheralPins.c
9- system_clock.c
109)
1110
1211target_include_directories (mbed-nucleo-wl55jc
Original file line number Diff line number Diff line change 1+ # Copyright (c) 2020 ARM Limited. All rights reserved.
2+ # SPDX-License-Identifier: Apache-2.0
3+
4+ if (${MBED_TOOLCHAIN} STREQUAL "GCC_ARM" )
5+ set (STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32wle5xx.S)
6+ set (LINKER_FILE TOOLCHAIN_GCC_ARM/stm32wle5xc.ld)
7+ elseif (${MBED_TOOLCHAIN} STREQUAL "ARM" )
8+ set (STARTUP_FILE TOOLCHAIN_ARM/startup_stm32wle5xx.S)
9+ set (LINKER_FILE TOOLCHAIN_ARM/stm32wle5xc.sct)
10+ endif ()
11+
12+ add_library (mbed-stm32wle5xc INTERFACE )
13+
14+ target_sources (mbed-stm32wle5xc
15+ INTERFACE
16+ ${STARTUP_FILE}
17+ )
18+
19+ target_include_directories (mbed-stm32wle5xc
20+ INTERFACE
21+ .
22+ )
23+
24+ mbed_set_linker_script(mbed-stm32wle5xc ${CMAKE_CURRENT_SOURCE_DIR} /${LINKER_FILE} )
25+
26+ target_link_libraries (mbed-stm32wle5xc INTERFACE mbed-stm32wl)
File renamed without changes.
Original file line number Diff line number Diff line change 43814381 ],
43824382 "device_name" : " STM32WL55JCIx"
43834383 },
4384+ "MCU_STM32WLE5xC" : {
4385+ "inherits" : [
4386+ " MCU_STM32WL"
4387+ ],
4388+ "public" : false ,
4389+ "macros_add" : [
4390+ " STM32WLE5xx"
4391+ ],
4392+ "extra_labels_add" : [
4393+ " STM32WLE5xC"
4394+ ],
4395+ "mbed_rom_start" : " 0x8000000" ,
4396+ "mbed_rom_size" : " 0x40000" ,
4397+ "mbed_ram_start" : " 0x20000000" ,
4398+ "mbed_ram_size" : " 0x10000"
4399+ },
43844400 "MIMXRT1050_EVK" : {
43854401 "supported_form_factors" : [
43864402 " ARDUINO_UNO"
Original file line number Diff line number Diff line change @@ -480222,6 +480222,142 @@
480222480222 ]
480223480223 ],
480224480224 "sub_family": "STM32WL55"
480225+ },
480226+ "STM32WLE5JCIx": {
480227+ "name": "STM32WLE5JCIx:CM4",
480228+ "memories": {
480229+ "IRAM1": {
480230+ "access": {
480231+ "read": true,
480232+ "write": true,
480233+ "execute": false,
480234+ "peripheral": false,
480235+ "secure": false,
480236+ "non_secure": false,
480237+ "non_secure_callable": false
480238+ },
480239+ "start": 536870912,
480240+ "size": 65536,
480241+ "startup": false,
480242+ "default": true
480243+ },
480244+ "IROM1": {
480245+ "access": {
480246+ "read": true,
480247+ "write": false,
480248+ "execute": true,
480249+ "peripheral": false,
480250+ "secure": false,
480251+ "non_secure": false,
480252+ "non_secure_callable": false
480253+ },
480254+ "start": 134217728,
480255+ "size": 262144,
480256+ "startup": true,
480257+ "default": true
480258+ }
480259+ },
480260+ "algorithms": [
480261+ {
480262+ "file_name": "CMSIS/Flash/STM32WLxx_CM4.FLM",
480263+ "start": 134217728,
480264+ "size": 262144,
480265+ "default": true,
480266+ "ram_start": null,
480267+ "ram_size": null
480268+ }
480269+ ],
480270+ "processor": {
480271+ "Symmetric": {
480272+ "units": 1,
480273+ "core": "CortexM4",
480274+ "fpu": "None",
480275+ "mpu": "Present"
480276+ }
480277+ },
480278+ "from_pack": {
480279+ "vendor": "Keil",
480280+ "pack": "STM32WLxx_DFP",
480281+ "version": "1.1.0",
480282+ "url": "http://www.keil.com/pack"
480283+ },
480284+ "vendor": "STMicroelectronics:13",
480285+ "family": "STM32WL Series",
480286+ "sectors": [
480287+ [
480288+ 134217728,
480289+ 2048
480290+ ]
480291+ ],
480292+ "sub_family": "STM32WLE5"
480293+ },
480294+ "STM32WLE5CCUx": {
480295+ "name": "STM32WLE5CCUx:CM4",
480296+ "memories": {
480297+ "IRAM1": {
480298+ "access": {
480299+ "read": true,
480300+ "write": true,
480301+ "execute": false,
480302+ "peripheral": false,
480303+ "secure": false,
480304+ "non_secure": false,
480305+ "non_secure_callable": false
480306+ },
480307+ "start": 536870912,
480308+ "size": 65536,
480309+ "startup": false,
480310+ "default": true
480311+ },
480312+ "IROM1": {
480313+ "access": {
480314+ "read": true,
480315+ "write": false,
480316+ "execute": true,
480317+ "peripheral": false,
480318+ "secure": false,
480319+ "non_secure": false,
480320+ "non_secure_callable": false
480321+ },
480322+ "start": 134217728,
480323+ "size": 262144,
480324+ "startup": true,
480325+ "default": true
480326+ }
480327+ },
480328+ "algorithms": [
480329+ {
480330+ "file_name": "CMSIS/Flash/STM32WLxx_CM4.FLM",
480331+ "start": 134217728,
480332+ "size": 262144,
480333+ "default": true,
480334+ "ram_start": null,
480335+ "ram_size": null
480336+ }
480337+ ],
480338+ "processor": {
480339+ "Symmetric": {
480340+ "units": 1,
480341+ "core": "CortexM4",
480342+ "fpu": "None",
480343+ "mpu": "Present"
480344+ }
480345+ },
480346+ "from_pack": {
480347+ "vendor": "Keil",
480348+ "pack": "STM32WLxx_DFP",
480349+ "version": "1.1.0",
480350+ "url": "http://www.keil.com/pack"
480351+ },
480352+ "vendor": "STMicroelectronics:13",
480353+ "family": "STM32WL Series",
480354+ "sectors": [
480355+ [
480356+ 134217728,
480357+ 2048
480358+ ]
480359+ ],
480360+ "sub_family": "STM32WLE5"
480225480361 },
480226480362 "STM32WB15CCUx": {
480227480363 "name": "STM32WB15CCUx",
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