Merge pull request #11950 from ABOSTM/DISCO_H747I_TICKLESS

0xc0170 · web-flow · commit 7177d8fefe26 · 2019-11-29T09:48:09.000+01:00
DISCO_H747I: add support of MBED_TICKLESS
diff --git a/features/mbedtls/targets/TARGET_STM/TARGET_STM32L4/aes_alt.c b/features/mbedtls/targets/TARGET_STM/TARGET_STM32L4/aes_alt.c
@@ -93,8 +93,7 @@ void mbedtls_aes_free(mbedtls_aes_context *ctx)
         return;
     }
 #if defined(DUAL_CORE)
-    uint32_t timeout = HSEM_TIMEOUT;
-    while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
+    while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
     }
 #endif /* DUAL_CORE */
     /* Force the CRYP Periheral Clock Reset */
diff --git a/targets/TARGET_STM/TARGET_STM32F0/common_objects.h b/targets/TARGET_STM/TARGET_STM32F0/common_objects.h
@@ -36,6 +36,7 @@
 #include "PinNames.h"
 #include "stm32f0xx_ll_usart.h"
 #include "stm32f0xx_ll_tim.h"
+#include "stm32f0xx_ll_pwr.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -119,6 +120,13 @@ struct analogin_s {
     uint8_t channel;
 };
 
+
+#ifdef CRC_PROG_POLYNOMIAL_SUPPORT
+#define HAL_CRC_IS_SUPPORTED(polynomial, width) ((width) == 7 || (width) == 8 || (width) == 16 || (width) == 32)
+#else
+#define HAL_CRC_IS_SUPPORTED(polynomial, width) ((width) == 32 && (polynomial) == 0x04C11DB7)
+#endif
+
 #include "gpio_object.h"
 
 #if DEVICE_ANALOGOUT
diff --git a/targets/TARGET_STM/TARGET_STM32F1/common_objects.h b/targets/TARGET_STM/TARGET_STM32F1/common_objects.h
@@ -36,6 +36,7 @@
 #include "PinNames.h"
 #include "stm32f1xx_ll_usart.h"
 #include "stm32f1xx_ll_tim.h"
+#include "stm32f1xx_ll_pwr.h"
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/targets/TARGET_STM/TARGET_STM32F2/objects.h b/targets/TARGET_STM/TARGET_STM32F2/objects.h
@@ -36,6 +36,7 @@
 #include "PinNames.h"
 #include "stm32f2xx_ll_usart.h"
 #include "stm32f2xx_ll_tim.h"
+#include "stm32f2xx_ll_pwr.h"
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/targets/TARGET_STM/TARGET_STM32F3/common_objects.h b/targets/TARGET_STM/TARGET_STM32F3/common_objects.h
@@ -36,6 +36,7 @@
 #include "PinNames.h"
 #include "stm32f3xx_ll_usart.h"
 #include "stm32f3xx_ll_tim.h"
+#include "stm32f3xx_ll_pwr.h"
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/targets/TARGET_STM/TARGET_STM32F4/common_objects.h b/targets/TARGET_STM/TARGET_STM32F4/common_objects.h
@@ -36,6 +36,7 @@
 #include "PinNames.h"
 #include "stm32f4xx_ll_usart.h"
 #include "stm32f4xx_ll_tim.h"
+#include "stm32f4xx_ll_pwr.h"
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/targets/TARGET_STM/TARGET_STM32F7/common_objects.h b/targets/TARGET_STM/TARGET_STM32F7/common_objects.h
@@ -38,6 +38,7 @@
 #include "stm32f7xx_ll_tim.h"
 #include "stm32f7xx_ll_adc.h"
 #include "stm32f7xx_ll_rtc.h"
+#include "stm32f7xx_ll_pwr.h"
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/h747i_sleep.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/h747i_sleep.c
diff --git a/targets/TARGET_STM/TARGET_STM32H7/analogin_device.c b/targets/TARGET_STM/TARGET_STM32H7/analogin_device.c
@@ -89,8 +89,7 @@ void analogin_init(analogin_t *obj, PinName pin)
     PeriphClkInitStruct.AdcClockSelection    = RCC_ADCCLKSOURCE_CLKP;
     PeriphClkInitStruct.PLL2.PLL2P           = 4;
 #if defined(DUAL_CORE)
-    uint32_t timeout = HSEM_TIMEOUT;
-    while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
+    while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
     }
 #endif /* DUAL_CORE */
     HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_rcc.c b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_rcc.c
@@ -803,7 +803,19 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruc
     }
     else
     {
-      return HAL_ERROR;
+      /* Do not return HAL_ERROR if request repeats the current configuration */
+      uint32_t temp1_pllckcfg = RCC->PLLCKSELR;
+      uint32_t temp2_pllckcfg = RCC->PLL1DIVR;
+      if(((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
+	 (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
+         ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) ||
+         (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) ||
+         ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) ||
+         ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) ||
+         ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct->PLL.PLLR - 1U)))
+      {
+        return HAL_ERROR;
+      }
     }
   }
   return HAL_OK;
diff --git a/targets/TARGET_STM/TARGET_STM32H7/flash_api.c b/targets/TARGET_STM/TARGET_STM32H7/flash_api.c
@@ -28,8 +28,7 @@ static uint32_t GetSectorBase(uint32_t SectorId, uint32_t BanksId);
 int32_t flash_init(flash_t *obj)
 {
 #if defined(DUAL_CORE)
-    uint32_t timeout = HSEM_TIMEOUT;
-    while (LL_HSEM_1StepLock(HSEM, CFG_HW_FLASH_SEMID) && (--timeout != 0)) {
+    while (LL_HSEM_1StepLock(HSEM, CFG_HW_FLASH_SEMID)) {
     }
 #endif /* DUAL_CORE */
     /* Clear pending flags (if any) */
@@ -58,8 +57,7 @@ int32_t flash_erase_sector(flash_t *obj, uint32_t address)
     }
 
 #if defined(DUAL_CORE)
-    uint32_t timeout = HSEM_TIMEOUT;
-    while (LL_HSEM_1StepLock(HSEM, CFG_HW_FLASH_SEMID) && (--timeout != 0)) {
+    while (LL_HSEM_1StepLock(HSEM, CFG_HW_FLASH_SEMID)) {
     }
 #endif /* DUAL_CORE */
     if (HAL_FLASH_Unlock() != HAL_OK) {
@@ -121,8 +119,7 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data,
     }
 
 #if defined(DUAL_CORE)
-    uint32_t timeout = HSEM_TIMEOUT;
-    while (LL_HSEM_1StepLock(HSEM, CFG_HW_FLASH_SEMID) && (--timeout != 0)) {
+    while (LL_HSEM_1StepLock(HSEM, CFG_HW_FLASH_SEMID)) {
     }
 #endif /* DUAL_CORE */
     if (HAL_FLASH_Unlock() != HAL_OK) {
diff --git a/targets/TARGET_STM/TARGET_STM32H7/objects.h b/targets/TARGET_STM/TARGET_STM32H7/objects.h
@@ -40,9 +40,9 @@
 #if defined(DUAL_CORE)
 #include "stm32h7xx_ll_hsem.h"
 #include "stm32h7xx_ll_rcc.h"
-#include "stm32h7xx_ll_pwr.h"
 #include "stm32h7xx_ll_cortex.h"
 #endif /* CONFIG_STM32H7_DUAL_CORE */
+#include "stm32h7xx_ll_pwr.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -151,8 +151,8 @@ struct analogin_s {
 #if defined(DUAL_CORE)
 /* HW semaphore Complement ID list defined in hw_conf.h from STM32WB */
 /* Index of the semaphore used to manage the entry Stop Mode procedure */
-#define CFG_HW_ENTRY_STOP_MODE_SEMID                            4
-#define CFG_HW_ENTRY_STOP_MODE_MASK_SEMID                      (1 << CFG_HW_ENTRY_STOP_MODE_SEMID)
+#define CFG_HW_STOP_MODE_SEMID                                  4
+#define CFG_HW_STOP_MODE_MASK_SEMID                            (1 << CFG_HW_STOP_MODE_SEMID)
 
 /* Index of the semaphore used to access the RCC */
 #define CFG_HW_RCC_SEMID                                        3
diff --git a/targets/TARGET_STM/TARGET_STM32H7/pin_device.h b/targets/TARGET_STM/TARGET_STM32H7/pin_device.h
@@ -45,8 +45,7 @@ static inline void stm_pin_DisconnectDebug(PinName pin)
 static inline void stm_pin_PullConfig(GPIO_TypeDef *gpio, uint32_t ll_pin, uint32_t pull_config)
 {
 #if defined(DUAL_CORE)
-    uint32_t timeout = HSEM_TIMEOUT;
-    while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID) && (--timeout != 0)) {
+    while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID)) {
     }
 #endif /* DUAL_CORE */
 
@@ -72,8 +71,7 @@ static inline void stm_pin_SetAFPin(GPIO_TypeDef *gpio, PinName pin, uint32_t af
     uint32_t ll_pin  = ll_pin_defines[STM_PIN(pin)];
 
 #if defined(DUAL_CORE)
-    uint32_t timeout = HSEM_TIMEOUT;
-    while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID) && (--timeout != 0)) {
+    while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID)) {
     }
 #endif /* DUAL_CORE */
 
diff --git a/targets/TARGET_STM/TARGET_STM32L0/common_objects.h b/targets/TARGET_STM/TARGET_STM32L0/common_objects.h
@@ -36,6 +36,7 @@
 #include "PinNames.h"
 #include "stm32l0xx_ll_usart.h"
 #include "stm32l0xx_ll_tim.h"
+#include "stm32l0xx_ll_pwr.h"
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/targets/TARGET_STM/TARGET_STM32L1/common_objects.h b/targets/TARGET_STM/TARGET_STM32L1/common_objects.h
@@ -36,6 +36,7 @@
 #include "PinNames.h"
 #include "stm32l1xx_ll_usart.h"
 #include "stm32l1xx_ll_tim.h"
+#include "stm32l1xx_ll_pwr.h"
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/targets/TARGET_STM/TARGET_STM32L4/common_objects.h b/targets/TARGET_STM/TARGET_STM32L4/common_objects.h
@@ -38,6 +38,7 @@
 #include "stm32l4xx_ll_lpuart.h"
 #include "stm32l4xx_ll_tim.h"
 #include "stm32l4xx_ll_rtc.h"
+#include "stm32l4xx_ll_pwr.h"
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/targets/TARGET_STM/TARGET_STM32WB/common_objects.h b/targets/TARGET_STM/TARGET_STM32WB/common_objects.h
@@ -38,6 +38,7 @@
 #include "PinNames.h"
 #include "stm32wbxx_ll_usart.h"
 #include "stm32wbxx_ll_tim.h"
+#include "stm32wbxx_ll_pwr.h"
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/targets/TARGET_STM/can_api.c b/targets/TARGET_STM/can_api.c
@@ -87,8 +87,7 @@ static void _can_init_freq_direct(can_t *obj, const can_pinmap_t *pinmap, int hz
     RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_FDCAN;
     RCC_PeriphClkInit.FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL; // 10 MHz (RCC_OscInitStruct.PLL.PLLQ = 80)
 #if defined(DUAL_CORE)
-    uint32_t timeout = HSEM_TIMEOUT;
-    while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
+    while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
     }
 #endif /* DUAL_CORE */
     if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
@@ -229,8 +228,7 @@ void can_irq_free(can_t *obj)
 void can_free(can_t *obj)
 {
 #if defined(DUAL_CORE)
-    uint32_t timeout = HSEM_TIMEOUT;
-    while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
+    while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
     }
 #endif /* DUAL_CORE */
     __HAL_RCC_FDCAN_FORCE_RESET();
@@ -716,8 +714,7 @@ void can_free(can_t *obj)
 {
     CANName can = (CANName) obj->CanHandle.Instance;
 #if defined(DUAL_CORE)
-    uint32_t timeout = HSEM_TIMEOUT;
-    while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
+    while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
     }
 #endif /* DUAL_CORE */
     // Reset CAN and disable clock
diff --git a/targets/TARGET_STM/gpio_api.c b/targets/TARGET_STM/gpio_api.c
@@ -156,8 +156,7 @@ void gpio_mode(gpio_t *obj, PinMode mode)
 inline void gpio_dir(gpio_t *obj, PinDirection direction)
 {
 #if defined(DUAL_CORE)
-    uint32_t timeout = HSEM_TIMEOUT;
-    while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID) && (--timeout != 0)) {
+    while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID)) {
     }
 #endif /* DUAL_CORE */
 
diff --git a/targets/TARGET_STM/gpio_object.h b/targets/TARGET_STM/gpio_object.h
@@ -58,8 +58,7 @@ typedef struct {
 static inline void gpio_write(gpio_t *obj, int value)
 {
 #if defined(DUAL_CORE)
-    uint32_t timeout = HSEM_TIMEOUT;
-    while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID) && (--timeout != 0)) {
+    while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID)) {
     }
 #endif /* DUAL_CORE */
 
diff --git a/targets/TARGET_STM/i2c_api.c b/targets/TARGET_STM/i2c_api.c
@@ -215,8 +215,7 @@ void i2c_hw_reset(i2c_t *obj)
     timeout = BYTE_TIMEOUT;
     while ((__HAL_I2C_GET_FLAG(handle, I2C_FLAG_BUSY)) && (--timeout != 0));
 #if defined(DUAL_CORE)
-    timeout = HSEM_TIMEOUT;
-    while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
+    while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
     }
 #endif /* DUAL_CORE */
 #if defined I2C1_BASE
@@ -452,8 +451,7 @@ void i2c_frequency(i2c_t *obj, int hz)
 
     /*##-1- Configure the I2C clock source. The clock is derived from the SYSCLK #*/
 #if defined(DUAL_CORE)
-    timeout = HSEM_TIMEOUT;
-    while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
+    while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
     }
 #endif /* DUAL_CORE */
 #if defined(I2C1_BASE) && defined (__HAL_RCC_I2C1_CONFIG)
diff --git a/targets/TARGET_STM/lp_ticker.c b/targets/TARGET_STM/lp_ticker.c
@@ -67,6 +67,13 @@
 #define LPTIM_MST_IRQ             LPTIM4_IRQn
 #define LPTIM_MST_RCC             __HAL_RCC_LPTIM4_CLK_ENABLE
 
+#define LPTIM_MST_RCC_CLKAM                  __HAL_RCC_LPTIM4_CLKAM_ENABLE
+
+/* Enable LPTIM wakeup source but only for current core, and disable it for the other core */
+#define LPTIM_MST_EXTI_LPTIM_WAKEUP_CONFIG()  {\
+                                                 HAL_EXTI_D1_EventInputConfig(EXTI_LINE52, EXTI_MODE_IT, ENABLE);\
+                                                 HAL_EXTI_D2_EventInputConfig(EXTI_LINE52, EXTI_MODE_IT, DISABLE);\
+                                               }
 #define LPTIM_MST_RESET_ON        __HAL_RCC_LPTIM4_FORCE_RESET
 #define LPTIM_MST_RESET_OFF       __HAL_RCC_LPTIM4_RELEASE_RESET
 
@@ -85,6 +92,13 @@
 #define LPTIM_MST_IRQ             LPTIM5_IRQn
 #define LPTIM_MST_RCC             __HAL_RCC_LPTIM5_CLK_ENABLE
 
+#define LPTIM_MST_RCC_CLKAM       __HAL_RCC_LPTIM5_CLKAM_ENABLE
+
+/* Enable LPTIM wakeup source but only for current core, and disable it for the other core */
+#define LPTIM_MST_EXTI_LPTIM_WAKEUP_CONFIG()  {\
+                                                 HAL_EXTI_D2_EventInputConfig(EXTI_LINE53, EXTI_MODE_IT, ENABLE);\
+                                                 HAL_EXTI_D1_EventInputConfig(EXTI_LINE53, EXTI_MODE_IT, DISABLE);\
+                                               }
 #define LPTIM_MST_RESET_ON        __HAL_RCC_LPTIM5_FORCE_RESET
 #define LPTIM_MST_RESET_OFF       __HAL_RCC_LPTIM5_RELEASE_RESET
 #else
@@ -191,8 +205,7 @@ void lp_ticker_init(void)
 
 #endif /* MBED_CONF_TARGET_LSE_AVAILABLE */
 #if defined(DUAL_CORE)
-    uint32_t timeout = HSEM_TIMEOUT;
-    while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
+    while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
     }
 #endif /* DUAL_CORE */
     if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
@@ -209,6 +222,10 @@ void lp_ticker_init(void)
     LPTIM_MST_RESET_ON();
     LPTIM_MST_RESET_OFF();
 #if defined(DUAL_CORE)
+    /* Configure EXTI wakeup and configure autonomous mode */
+    LPTIM_MST_RCC_CLKAM();
+    LPTIM_MST_EXTI_LPTIM_WAKEUP_CONFIG();
+
     LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT);
 #endif /* DUAL_CORE */
 
diff --git a/targets/TARGET_STM/mbed_overrides.c b/targets/TARGET_STM/mbed_overrides.c
@@ -60,7 +60,7 @@ void mbed_sdk_init()
         /* CM4 boots at the same time than CM7. It is necessary to synchronize with CM7, by mean of HSEM, that CM7 finishes its initialization.  */
 
         /* Activate HSEM notification for Cortex-M4*/
-        LL_HSEM_EnableIT_C2IER(HSEM, CFG_HW_ENTRY_STOP_MODE_MASK_SEMID);
+        LL_HSEM_EnableIT_C2IER(HSEM, CFG_HW_STOP_MODE_MASK_SEMID);
 
         /*
         * Domain D2 goes to STOP mode (Cortex-M4 in deep-sleep) waiting for
@@ -89,7 +89,8 @@ void mbed_sdk_init()
         LL_LPM_EnableSleep();
 
         /* Clear HSEM flag */
-        LL_HSEM_ClearFlag_C2ICR(HSEM, CFG_HW_ENTRY_STOP_MODE_MASK_SEMID);
+        LL_HSEM_DisableIT_C2IER(HSEM, CFG_HW_STOP_MODE_MASK_SEMID);
+        LL_HSEM_ClearFlag_C2ICR(HSEM, CFG_HW_STOP_MODE_MASK_SEMID);
     }
 
     // Update the SystemCoreClock variable.
@@ -109,9 +110,9 @@ void mbed_sdk_init()
     /* Check wether CM4 boot in parallel with CM7. If CM4 was gated but CM7 trigger the CM4 boot. No need to wait for synchronization.
        otherwise CM7 should wakeup CM4 when system clocks initialization is done.  */
     if (READ_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM4)) {
-        LL_HSEM_1StepLock(HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID);
+        LL_HSEM_1StepLock(HSEM, CFG_HW_STOP_MODE_SEMID);
         /*Release HSEM in order to notify the CPU2(CM4)*/
-        LL_HSEM_ReleaseLock(HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID, 0);
+        LL_HSEM_ReleaseLock(HSEM, CFG_HW_STOP_MODE_SEMID, 0);
     } else {
         LL_RCC_ForceCM4Boot();
     }
diff --git a/targets/TARGET_STM/pinmap.c b/targets/TARGET_STM/pinmap.c
diff --git a/targets/TARGET_STM/qspi_api.c b/targets/TARGET_STM/qspi_api.c
diff --git a/targets/TARGET_STM/rtc_api.c b/targets/TARGET_STM/rtc_api.c
diff --git a/targets/TARGET_STM/serial_api.c b/targets/TARGET_STM/serial_api.c
diff --git a/targets/TARGET_STM/sleep.c b/targets/TARGET_STM/sleep.c
diff --git a/targets/TARGET_STM/stm_spi_api.c b/targets/TARGET_STM/stm_spi_api.c
diff --git a/targets/TARGET_STM/trng_api.c b/targets/TARGET_STM/trng_api.c
diff --git a/targets/TARGET_STM/us_ticker.c b/targets/TARGET_STM/us_ticker.c
diff --git a/targets/targets.json b/targets/targets.json
diff --git a/tools/export/iar/iar_definitions.json b/tools/export/iar/iar_definitions.json

Original file line number	Diff line number	Diff line change
`@@ -93,8 +93,7 @@ void mbedtls_aes_free(mbedtls_aes_context *ctx)`
`93`	`93`	`return;`
`94`	`94`	`}`
`95`	`95`	`#if defined(DUAL_CORE)`
`96`		`- uint32_t timeout = HSEM_TIMEOUT;`
`97`		`- while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {`
	`96`	`+ while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {`
`98`	`97`	`}`
`99`	`98`	`#endif /* DUAL_CORE */`
`100`	`99`	`/* Force the CRYP Periheral Clock Reset */`
Original file line number	Diff line number	Diff line change
`@@ -803,7 +803,19 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc`
`803`	`803`	`}`
`804`	`804`	`else`
`805`	`805`	`{`
`806`		`- return HAL_ERROR;`
	`806`	`+ /* Do not return HAL_ERROR if request repeats the current configuration */`
	`807`	`+ uint32_t temp1_pllckcfg = RCC->PLLCKSELR;`
	`808`	`+ uint32_t temp2_pllckcfg = RCC->PLL1DIVR;`
	`809`	`+ if(((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) \|\|`
	`810`	`+ (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) \|\|`
	`811`	`+ ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) \|\|`
	`812`	`+ (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) \|\|`
	`813`	`+ ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) \|\|`
	`814`	`+ ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) \|\|`
	`815`	`+ ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct->PLL.PLLR - 1U)))`
	`816`	`+ {`
	`817`	`+ return HAL_ERROR;`
	`818`	`+ }`
`807`	`819`	`}`
`808`	`820`	`}`
`809`	`821`	`return HAL_OK;`