Fix fpga test function names

Author: mprse

TESTS/mbed_hal_fpga_ci_test_shield/gpio/main.cpp

@@ -225,14 +225,14 @@ void fpga_test_explicit_output(PinName pin)
 }
 
 Case cases[] = {
-    Case("generic init, input & output", all_ports<GPIOPort, DefaultFormFactor, test_basic_input_output>),
+    Case("generic init, input & output", all_ports<GPIOPort, DefaultFormFactor, fpga_test_basic_input_output>),
     // Some targets don't support input pull mode.
 #if !defined(TARGET_NANO100) &&         \
     !defined(TARGET_NUC472) &&          \
     !defined(TARGET_M451)
-    Case("explicit init, input", all_ports<GPIOPort, DefaultFormFactor, test_explicit_input>),
+    Case("explicit init, input", all_ports<GPIOPort, DefaultFormFactor, fpga_test_explicit_input>),
 #endif
-    Case("explicit init, output", all_ports<GPIOPort, DefaultFormFactor, test_explicit_output>),
+    Case("explicit init, output", all_ports<GPIOPort, DefaultFormFactor, fpga_test_explicit_output>),
 };
 
 utest::v1::status_t greentea_test_setup(const size_t number_of_cases)

TESTS/mbed_hal_fpga_ci_test_shield/spi/main.cpp

@@ -179,7 +179,7 @@ Case cases[] = {
     Case("SPI - mode testing (MODE_2)", one_peripheral<SPIPort, DefaultFormFactor, fpga_spi_test_common<SPITester::Mode2, 8, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_1_MHZ> >),
     Case("SPI - mode testing (MODE_3)", one_peripheral<SPIPort, DefaultFormFactor, fpga_spi_test_common<SPITester::Mode3, 8, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_1_MHZ> >),
 
-    Case("SPI - symbol size testing (16)", one_peripheral<SPIPort, DefaultFormFactor, spi_test_common<SPITester::Mode0, 16, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_1_MHZ> >),
+    Case("SPI - symbol size testing (16)", one_peripheral<SPIPort, DefaultFormFactor, fpga_spi_test_common<SPITester::Mode0, 16, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_1_MHZ> >),
 
     Case("SPI - frequency testing (500 kHz)", one_peripheral<SPIPort, DefaultFormFactor, fpga_spi_test_common<SPITester::Mode0, 8, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_500_KHZ> >),
     Case("SPI - frequency testing (2 MHz)", one_peripheral<SPIPort, DefaultFormFactor, fpga_spi_test_common<SPITester::Mode0, 8, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_2_MHZ> >),

TESTS/mbed_hal_fpga_ci_test_shield/uart/main.cpp

@@ -81,7 +81,7 @@ static void test_irq_handler(uint32_t id, SerialIrq event)
     }
 }
 
-static void uart_test_common(int baudrate, int data_bits, SerialParity parity, int stop_bits, PinName tx, PinName rx, PinName cts = NC, PinName rts = NC)
+static void uart_test_common(int baudrate, int data_bits, SerialParity parity, int stop_bits, PinName tx, PinName rx, PinName cts, PinName rts)
 {
     // The FPGA CI shield only supports None, Odd & Even.
     // Forced parity is not supported on Atmel, Freescale, Nordic & STM targets.
@@ -273,7 +273,7 @@ static void uart_test_common(int baudrate, int data_bits, SerialParity parity, i
     tester.reset();
 }
 
-void fpga_uart_init_free_test(PinName tx, PinName rx, PinName cts = NC, PinName rts = NC)
+void fpga_uart_init_free_test(PinName tx, PinName rx, PinName cts, PinName rts)
 {
     bool use_flow_control = (cts != NC && rts != NC) ? true : false;
     serial_t serial;