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JeanMarcRJeanMarcR
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STM32WL : ADDING STM32 SUPPORT
Add code concerning all STM32 platforms
1 parent e6565a4 commit 5a2835c

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17 files changed

+74
-60
lines changed

17 files changed

+74
-60
lines changed

‎targets/TARGET_STM/CMakeLists.txt‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,7 @@ add_subdirectory(TARGET_STM32L1 EXCLUDE_FROM_ALL)
1515
add_subdirectory(TARGET_STM32L4 EXCLUDE_FROM_ALL)
1616
add_subdirectory(TARGET_STM32L5 EXCLUDE_FROM_ALL)
1717
add_subdirectory(TARGET_STM32WB EXCLUDE_FROM_ALL)
18+
add_subdirectory(TARGET_STM32WL EXCLUDE_FROM_ALL)
1819

1920
add_library(STM INTERFACE)
2021

‎targets/TARGET_STM/can_api.c‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -92,14 +92,14 @@ static void _can_init_freq_direct(can_t *obj, const can_pinmap_t *pinmap, int hz
9292
RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit;
9393
RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_FDCAN;
9494
RCC_PeriphClkInit.FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL; // 10 MHz (RCC_OscInitStruct.PLL.PLLQ = 80)
95-
#if defined(DUAL_CORE)
95+
#if defined(DUAL_CORE) && (TARGET_STM32H7)
9696
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
9797
}
9898
#endif /* DUAL_CORE */
9999
if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
100100
error("HAL_RCCEx_PeriphCLKConfig error\n");
101101
}
102-
#if defined(DUAL_CORE)
102+
#if defined(DUAL_CORE) && (TARGET_STM32H7)
103103
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT);
104104
#endif /* DUAL_CORE */
105105
// Configure CAN pins
@@ -247,13 +247,13 @@ void can_irq_free(can_t *obj)
247247

248248
void can_free(can_t *obj)
249249
{
250-
#if defined(DUAL_CORE)
250+
#if defined(DUAL_CORE) && (TARGET_STM32H7)
251251
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
252252
}
253253
#endif /* DUAL_CORE */
254254
__HAL_RCC_FDCAN_FORCE_RESET();
255255
__HAL_RCC_FDCAN_RELEASE_RESET();
256-
#if defined(DUAL_CORE)
256+
#if defined(DUAL_CORE) && (TARGET_STM32H7)
257257
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT);
258258
#endif /* DUAL_CORE */
259259
__HAL_RCC_FDCAN_CLK_DISABLE();
@@ -772,7 +772,7 @@ void can_irq_free(can_t *obj)
772772
void can_free(can_t *obj)
773773
{
774774
CANName can = (CANName) obj->CanHandle.Instance;
775-
#if defined(DUAL_CORE)
775+
#if defined(DUAL_CORE) && (TARGET_STM32H7)
776776
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
777777
}
778778
#endif /* DUAL_CORE */
@@ -796,7 +796,7 @@ void can_free(can_t *obj)
796796
__HAL_RCC_CAN3_CLK_DISABLE();
797797
}
798798
#endif
799-
#if defined(DUAL_CORE)
799+
#if defined(DUAL_CORE) && (TARGET_STM32H7)
800800
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT);
801801
#endif /* DUAL_CORE */
802802
}

‎targets/TARGET_STM/gpio_api.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -170,7 +170,7 @@ void gpio_mode(gpio_t *obj, PinMode mode)
170170

171171
inline void gpio_dir(gpio_t *obj, PinDirection direction)
172172
{
173-
#if defined(DUAL_CORE)
173+
#if defined(DUAL_CORE) && (TARGET_STM32H7)
174174
while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID)) {
175175
}
176176
#endif /* DUAL_CORE */
@@ -181,7 +181,7 @@ inline void gpio_dir(gpio_t *obj, PinDirection direction)
181181
LL_GPIO_SetPinMode(obj->gpio, obj->ll_pin, LL_GPIO_MODE_OUTPUT);
182182
}
183183

184-
#if defined(DUAL_CORE)
184+
#if defined(DUAL_CORE) && (TARGET_STM32H7)
185185
LL_HSEM_ReleaseLock(HSEM, CFG_HW_GPIO_SEMID, HSEM_CR_COREID_CURRENT);
186186
#endif /* DUAL_CORE */
187187
}

‎targets/TARGET_STM/gpio_irq_api.c‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -149,7 +149,7 @@ static void handle_interrupt_in(uint32_t irq_index, uint32_t max_num_pin_line)
149149
#else /* TARGET_STM32L5 */
150150

151151
// Clear interrupt flag
152-
#if defined(DUAL_CORE) && defined(CORE_CM4)
152+
#if defined(DUAL_CORE) && defined(CORE_CM4) && defined(TARGET_STM32H7)
153153
if (__HAL_GPIO_EXTID2_GET_FLAG(pin) != RESET) {
154154
__HAL_GPIO_EXTID2_CLEAR_FLAG(pin);
155155
#else
@@ -323,7 +323,7 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32
323323
core_util_critical_section_enter();
324324

325325
/* Enable SYSCFG Clock */
326-
#if !defined(TARGET_STM32WB)
326+
#if (!defined(TARGET_STM32WB) && !defined(TARGET_STM32WL))
327327
__HAL_RCC_SYSCFG_CLK_ENABLE();
328328
#endif
329329

@@ -503,7 +503,7 @@ void gpio_irq_enable(gpio_irq_t *obj)
503503
SYSCFG->EXTICR[pin_index >> 2] = temp;
504504
#endif
505505

506-
#if defined(DUAL_CORE) && defined(CORE_CM4)
506+
#if defined(DUAL_CORE) && defined(CORE_CM4) && defined(TARGET_STM32H7)
507507
LL_C2_EXTI_EnableIT_0_31(1 << pin_index);
508508
#else
509509
LL_EXTI_EnableIT_0_31(1 << pin_index);
@@ -532,7 +532,7 @@ void gpio_irq_disable(gpio_irq_t *obj)
532532
LL_EXTI_DisableRisingTrig_0_31(1 << pin_index);
533533
LL_EXTI_DisableFallingTrig_0_31(1 << pin_index);
534534

535-
#if defined(DUAL_CORE) && defined(CORE_CM4)
535+
#if defined(DUAL_CORE) && defined(CORE_CM4) && defined(TARGET_STM32H7)
536536
LL_C2_EXTI_DisableIT_0_31(1 << pin_index);
537537
#else
538538
LL_EXTI_DisableIT_0_31(1 << pin_index);

‎targets/TARGET_STM/gpio_object.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -57,7 +57,7 @@ typedef struct {
5757

5858
static inline void gpio_write(gpio_t *obj, int value)
5959
{
60-
#if defined(DUAL_CORE)
60+
#if defined(DUAL_CORE) && (TARGET_STM32H7)
6161
while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID)) {
6262
}
6363
#endif /* DUAL_CORE */
@@ -72,7 +72,7 @@ static inline void gpio_write(gpio_t *obj, int value)
7272
#endif
7373
}
7474

75-
#if defined(DUAL_CORE)
75+
#if defined(DUAL_CORE) && (TARGET_STM32H7)
7676
LL_HSEM_ReleaseLock(HSEM, CFG_HW_GPIO_SEMID, HSEM_CR_COREID_CURRENT);
7777
#endif /* DUAL_CORE */
7878
}

‎targets/TARGET_STM/i2c_api.c‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -214,7 +214,7 @@ void i2c_hw_reset(i2c_t *obj)
214214
// wait before reset
215215
timeout = BYTE_TIMEOUT;
216216
while ((__HAL_I2C_GET_FLAG(handle, I2C_FLAG_BUSY)) && (--timeout != 0));
217-
#if defined(DUAL_CORE)
217+
#if defined(DUAL_CORE) && (TARGET_STM32H7)
218218
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
219219
}
220220
#endif /* DUAL_CORE */
@@ -248,7 +248,7 @@ void i2c_hw_reset(i2c_t *obj)
248248
__HAL_RCC_FMPI2C1_RELEASE_RESET();
249249
}
250250
#endif
251-
#if defined(DUAL_CORE)
251+
#if defined(DUAL_CORE) && (TARGET_STM32H7)
252252
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT);
253253
#endif /* DUAL_CORE */
254254
}
@@ -497,7 +497,7 @@ void i2c_frequency(i2c_t *obj, int hz)
497497
#endif //I2C_IP_VERSION_V2
498498

499499
/*##-1- Configure the I2C clock source. The clock is derived from the SYSCLK #*/
500-
#if defined(DUAL_CORE)
500+
#if defined(DUAL_CORE) && (TARGET_STM32H7)
501501
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
502502
}
503503
#endif /* DUAL_CORE */
@@ -521,7 +521,7 @@ void i2c_frequency(i2c_t *obj, int hz)
521521
__HAL_RCC_I2C4_CONFIG(I2CAPI_I2C4_CLKSRC);
522522
}
523523
#endif
524-
#if defined(DUAL_CORE)
524+
#if defined(DUAL_CORE) && (TARGET_STM32H7)
525525
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT);
526526
#endif /* DUAL_CORE */
527527

‎targets/TARGET_STM/lp_ticker.c‎

Lines changed: 8 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -55,7 +55,7 @@
5555
#define LP_TIMER_SAFE_GUARD 5
5656

5757

58-
#if defined(DUAL_CORE)
58+
#if defined(DUAL_CORE) && (TARGET_STM32H7)
5959
#if defined(CORE_CM7)
6060
#define LPTIM_MST_BASE LPTIM4_BASE
6161
#define LPTIM_MST ((LPTIM_TypeDef *)LPTIM_MST_BASE)
@@ -212,7 +212,7 @@ void lp_ticker_init(void)
212212
#endif /* TARGET_STM32L0 */
213213

214214
#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */
215-
#if defined(DUAL_CORE)
215+
#if defined(DUAL_CORE) && (TARGET_STM32H7)
216216
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
217217
}
218218
#endif /* DUAL_CORE */
@@ -229,7 +229,7 @@ void lp_ticker_init(void)
229229
LPTIM_MST_RCC();
230230
LPTIM_MST_RESET_ON();
231231
LPTIM_MST_RESET_OFF();
232-
#if defined(DUAL_CORE)
232+
#if defined(DUAL_CORE) && (TARGET_STM32H7)
233233
/* Configure EXTI wakeup and configure autonomous mode */
234234
LPTIM_MST_RCC_CLKAM();
235235
LPTIM_MST_EXTI_LPTIM_WAKEUP_CONFIG();
@@ -283,6 +283,11 @@ void lp_ticker_init(void)
283283

284284
NVIC_SetVector(LPTIM_MST_IRQ, (uint32_t)LPTIM_IRQHandler);
285285

286+
#if (LPTIM_MST_BASE == LPTIM1_BASE)
287+
#if defined (__HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT)
288+
__HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT();
289+
#endif
290+
#endif
286291
#if defined (__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT)
287292
/* EXTI lines are not configured by default */
288293
__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT();

‎targets/TARGET_STM/mbed_overrides.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -179,7 +179,7 @@ void mbed_sdk_init()
179179
}
180180
#endif /* __ICACHE_PRESENT */
181181

182-
#if defined(DUAL_CORE)
182+
#if defined(DUAL_CORE) && (TARGET_STM32H7)
183183
/* HW semaphore Clock enable*/
184184
__HAL_RCC_HSEM_CLK_ENABLE();
185185

‎targets/TARGET_STM/pinmap.c‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -82,7 +82,7 @@ void pin_function(PinName pin, int data)
8282
#if defined (TARGET_STM32F1)
8383
if (mode == STM_PIN_OUTPUT) {
8484
#endif
85-
#if defined(DUAL_CORE)
85+
#if defined(DUAL_CORE) && (TARGET_STM32H7)
8686
while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID)) {
8787
}
8888
#endif /* DUAL_CORE */
@@ -99,7 +99,7 @@ void pin_function(PinName pin, int data)
9999
LL_GPIO_SetPinSpeed(gpio, ll_pin, speed);
100100
break;
101101
}
102-
#if defined(DUAL_CORE)
102+
#if defined(DUAL_CORE) && (TARGET_STM32H7)
103103
LL_HSEM_ReleaseLock(HSEM, CFG_HW_GPIO_SEMID, HSEM_CR_COREID_CURRENT);
104104
#endif /* DUAL_CORE */
105105
#if defined (TARGET_STM32F1)
@@ -126,7 +126,7 @@ void pin_function(PinName pin, int data)
126126
break;
127127
}
128128

129-
#if defined(DUAL_CORE)
129+
#if defined(DUAL_CORE) && (TARGET_STM32H7)
130130
while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID)) {
131131
}
132132
#endif /* DUAL_CORE */
@@ -155,7 +155,7 @@ void pin_function(PinName pin, int data)
155155

156156
stm_pin_DisconnectDebug(pin);
157157

158-
#if defined(DUAL_CORE)
158+
#if defined(DUAL_CORE) && (TARGET_STM32H7)
159159
LL_HSEM_ReleaseLock(HSEM, CFG_HW_GPIO_SEMID, HSEM_CR_COREID_CURRENT);
160160
#endif /* DUAL_CORE */
161161
}
@@ -174,7 +174,7 @@ void pin_mode(PinName pin, PinMode mode)
174174
// Enable GPIO clock
175175
GPIO_TypeDef *gpio = Set_GPIO_Clock(port_index);
176176

177-
#if defined(DUAL_CORE)
177+
#if defined(DUAL_CORE) && (TARGET_STM32H7)
178178
while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID)) {
179179
}
180180
#endif /* DUAL_CORE */
@@ -197,7 +197,7 @@ void pin_mode(PinName pin, PinMode mode)
197197
stm_pin_PullConfig(gpio, ll_pin, GPIO_NOPULL);
198198
}
199199

200-
#if defined(DUAL_CORE)
200+
#if defined(DUAL_CORE) && (TARGET_STM32H7)
201201
LL_HSEM_ReleaseLock(HSEM, CFG_HW_GPIO_SEMID, HSEM_CR_COREID_CURRENT);
202202
#endif /* DUAL_CORE */
203203
}

‎targets/TARGET_STM/qspi_api.c‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -540,13 +540,13 @@ static qspi_status_t _qspi_init_direct(qspi_t *obj, const qspi_pinmap_t *pinmap,
540540
__HAL_RCC_QSPI_CLK_ENABLE();
541541

542542
// Reset QSPI
543-
#if defined(DUAL_CORE)
543+
#if defined(DUAL_CORE) && (TARGET_STM32H7)
544544
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
545545
}
546546
#endif /* DUAL_CORE */
547547
__HAL_RCC_QSPI_FORCE_RESET();
548548
__HAL_RCC_QSPI_RELEASE_RESET();
549-
#if defined(DUAL_CORE)
549+
#if defined(DUAL_CORE) && (TARGET_STM32H7)
550550
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT);
551551
#endif /* DUAL_CORE */
552552

@@ -675,13 +675,13 @@ qspi_status_t qspi_free(qspi_t *obj)
675675
}
676676

677677
// Reset QSPI
678-
#if defined(DUAL_CORE)
678+
#if defined(DUAL_CORE) && (TARGET_STM32H7)
679679
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
680680
}
681681
#endif /* DUAL_CORE */
682682
__HAL_RCC_QSPI_FORCE_RESET();
683683
__HAL_RCC_QSPI_RELEASE_RESET();
684-
#if defined(DUAL_CORE)
684+
#if defined(DUAL_CORE) && (TARGET_STM32H7)
685685
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT);
686686
#endif /* DUAL_CORE */
687687

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