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polat-ahmetozersa
polat-ahmet
authored and
ozersa
committed
Update MAX32660 peripheral drivers with final ones that use by SDK
1 parent d0ca14e commit 3f4b177

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‎targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/dma_regs.h‎

Lines changed: 184 additions & 186 deletions
Large diffs are not rendered by default.

‎targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/fcr_regs.h‎

Lines changed: 23 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,11 @@
11
/**
22
* @file fcr_regs.h
33
* @brief Registers, Bit Masks and Bit Positions for the FCR Peripheral Module.
4+
* @note This file is @generated.
45
*/
56

6-
/* ****************************************************************************
7-
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
7+
/******************************************************************************
8+
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
89
*
910
* Permission is hereby granted, free of charge, to any person obtaining a
1011
* copy of this software and associated documentation files (the "Software"),
@@ -34,23 +35,22 @@
3435
* property whatsoever. Maxim Integrated Products, Inc. retains all
3536
* ownership rights.
3637
*
37-
*
38-
*************************************************************************** */
38+
******************************************************************************/
3939

40-
#ifndef _FCR_REGS_H_
41-
#define _FCR_REGS_H_
40+
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_FCR_REGS_H_
41+
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_FCR_REGS_H_
4242

4343
/* **** Includes **** */
4444
#include <stdint.h>
4545

4646
#ifdef __cplusplus
4747
extern "C" {
4848
#endif
49-
49+
5050
#if defined (__ICCARM__)
5151
#pragma system_include
5252
#endif
53-
53+
5454
#if defined (__CC_ARM)
5555
#pragma anon_unions
5656
#endif
@@ -67,7 +67,9 @@ extern "C" {
6767
#ifndef __O
6868
#define __O volatile
6969
#endif
70-
70+
#ifndef __R
71+
#define __R volatile const
72+
#endif
7173
/// @endcond
7274

7375
/* **** Definitions **** */
@@ -76,7 +78,7 @@ extern "C" {
7678
* @ingroup fcr
7779
* @defgroup fcr_registers FCR_Registers
7880
* @brief Registers, Bit Masks and Bit Positions for the FCR Peripheral Module.
79-
* @details Function Control.
81+
* @details Function Control.
8082
*/
8183

8284
/**
@@ -91,10 +93,10 @@ typedef struct {
9193
/**
9294
* @ingroup fcr_registers
9395
* @defgroup FCR_Register_Offsets Register Offsets
94-
* @brief FCR Peripheral Register Offsets from the FCR Base Peripheral Address.
96+
* @brief FCR Peripheral Register Offsets from the FCR Base Peripheral Address.
9597
* @{
9698
*/
97-
#define MXC_R_FCR_REG0 ((uint32_t)0x00000000UL) /**< Offset from FCR Base Address: <tt> 0x0000</tt> */
99+
#define MXC_R_FCR_REG0 ((uint32_t)0x00000000UL) /**< Offset from FCR Base Address: <tt> 0x0000</tt> */
98100
/**@} end of group fcr_registers */
99101

100102
/**
@@ -103,22 +105,22 @@ typedef struct {
103105
* @brief Register 0.
104106
* @{
105107
*/
106-
#define MXC_F_FCR_REG0_I2C0_SDA_FILTER_EN_POS 20 /**< REG0_I2C0_SDA_FILTER_EN Position */
107-
#define MXC_F_FCR_REG0_I2C0_SDA_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_REG0_I2C0_SDA_FILTER_EN_POS)) /**< REG0_I2C0_SDA_FILTER_EN Mask */
108+
#define MXC_F_FCR_REG0_I2C0_SDA_FILTER_EN_POS 20 /**< REG0_I2C0_SDA_FILTER_EN Position */
109+
#define MXC_F_FCR_REG0_I2C0_SDA_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_REG0_I2C0_SDA_FILTER_EN_POS)) /**< REG0_I2C0_SDA_FILTER_EN Mask */
108110

109-
#define MXC_F_FCR_REG0_I2C0_SCL_FILTER_EN_POS 21 /**< REG0_I2C0_SCL_FILTER_EN Position */
110-
#define MXC_F_FCR_REG0_I2C0_SCL_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_REG0_I2C0_SCL_FILTER_EN_POS)) /**< REG0_I2C0_SCL_FILTER_EN Mask */
111+
#define MXC_F_FCR_REG0_I2C0_SCL_FILTER_EN_POS 21 /**< REG0_I2C0_SCL_FILTER_EN Position */
112+
#define MXC_F_FCR_REG0_I2C0_SCL_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_REG0_I2C0_SCL_FILTER_EN_POS)) /**< REG0_I2C0_SCL_FILTER_EN Mask */
111113

112-
#define MXC_F_FCR_REG0_I2C1_SDA_FILTER_EN_POS 22 /**< REG0_I2C1_SDA_FILTER_EN Position */
113-
#define MXC_F_FCR_REG0_I2C1_SDA_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_REG0_I2C1_SDA_FILTER_EN_POS)) /**< REG0_I2C1_SDA_FILTER_EN Mask */
114+
#define MXC_F_FCR_REG0_I2C1_SDA_FILTER_EN_POS 22 /**< REG0_I2C1_SDA_FILTER_EN Position */
115+
#define MXC_F_FCR_REG0_I2C1_SDA_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_REG0_I2C1_SDA_FILTER_EN_POS)) /**< REG0_I2C1_SDA_FILTER_EN Mask */
114116

115-
#define MXC_F_FCR_REG0_I2C1_SCL_FILTER_EN_POS 23 /**< REG0_I2C1_SCL_FILTER_EN Position */
116-
#define MXC_F_FCR_REG0_I2C1_SCL_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_REG0_I2C1_SCL_FILTER_EN_POS)) /**< REG0_I2C1_SCL_FILTER_EN Mask */
117+
#define MXC_F_FCR_REG0_I2C1_SCL_FILTER_EN_POS 23 /**< REG0_I2C1_SCL_FILTER_EN Position */
118+
#define MXC_F_FCR_REG0_I2C1_SCL_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_REG0_I2C1_SCL_FILTER_EN_POS)) /**< REG0_I2C1_SCL_FILTER_EN Mask */
117119

118120
/**@} end of group FCR_REG0_Register */
119121

120122
#ifdef __cplusplus
121123
}
122124
#endif
123125

124-
#endif /* _FCR_REGS_H_ */
126+
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_FCR_REGS_H_

‎targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/flc_regs.h‎

Lines changed: 64 additions & 62 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,11 @@
11
/**
22
* @file flc_regs.h
33
* @brief Registers, Bit Masks and Bit Positions for the FLC Peripheral Module.
4+
* @note This file is @generated.
45
*/
56

6-
/* ****************************************************************************
7-
* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved.
7+
/******************************************************************************
8+
* Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved.
89
*
910
* Permission is hereby granted, free of charge, to any person obtaining a
1011
* copy of this software and associated documentation files (the "Software"),
@@ -34,23 +35,22 @@
3435
* property whatsoever. Maxim Integrated Products, Inc. retains all
3536
* ownership rights.
3637
*
37-
*
38-
*************************************************************************** */
38+
******************************************************************************/
3939

40-
#ifndef _FLC_REGS_H_
41-
#define _FLC_REGS_H_
40+
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_FLC_REGS_H_
41+
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_FLC_REGS_H_
4242

4343
/* **** Includes **** */
4444
#include <stdint.h>
4545

4646
#ifdef __cplusplus
4747
extern "C" {
4848
#endif
49-
49+
5050
#if defined (__ICCARM__)
5151
#pragma system_include
5252
#endif
53-
53+
5454
#if defined (__CC_ARM)
5555
#pragma anon_unions
5656
#endif
@@ -67,7 +67,9 @@ extern "C" {
6767
#ifndef __O
6868
#define __O volatile
6969
#endif
70-
70+
#ifndef __R
71+
#define __R volatile const
72+
#endif
7173
/// @endcond
7274

7375
/* **** Definitions **** */
@@ -76,7 +78,7 @@ extern "C" {
7678
* @ingroup flc
7779
* @defgroup flc_registers FLC_Registers
7880
* @brief Registers, Bit Masks and Bit Positions for the FLC Peripheral Module.
79-
* @details Flash Memory Control.
81+
* @details Flash Memory Control.
8082
*/
8183

8284
/**
@@ -87,9 +89,9 @@ typedef struct {
8789
__IO uint32_t addr; /**< <tt>\b 0x00:</tt> FLC ADDR Register */
8890
__IO uint32_t clkdiv; /**< <tt>\b 0x04:</tt> FLC CLKDIV Register */
8991
__IO uint32_t ctrl; /**< <tt>\b 0x08:</tt> FLC CTRL Register */
90-
__I uint32_t rsv_0xc_0x23[6];
92+
__R uint32_t rsv_0xc_0x23[6];
9193
__IO uint32_t intr; /**< <tt>\b 0x024:</tt> FLC INTR Register */
92-
__I uint32_t rsv_0x28_0x2f[2];
94+
__R uint32_t rsv_0x28_0x2f[2];
9395
__IO uint32_t data[4]; /**< <tt>\b 0x30:</tt> FLC DATA Register */
9496
__O uint32_t actrl; /**< <tt>\b 0x40:</tt> FLC ACTRL Register */
9597
} mxc_flc_regs_t;
@@ -98,15 +100,15 @@ typedef struct {
98100
/**
99101
* @ingroup flc_registers
100102
* @defgroup FLC_Register_Offsets Register Offsets
101-
* @brief FLC Peripheral Register Offsets from the FLC Base Peripheral Address.
103+
* @brief FLC Peripheral Register Offsets from the FLC Base Peripheral Address.
102104
* @{
103105
*/
104-
#define MXC_R_FLC_ADDR ((uint32_t)0x00000000UL) /**< Offset from FLC Base Address: <tt> 0x0000</tt> */
105-
#define MXC_R_FLC_CLKDIV ((uint32_t)0x00000004UL) /**< Offset from FLC Base Address: <tt> 0x0004</tt> */
106-
#define MXC_R_FLC_CTRL ((uint32_t)0x00000008UL) /**< Offset from FLC Base Address: <tt> 0x0008</tt> */
107-
#define MXC_R_FLC_INTR ((uint32_t)0x00000024UL) /**< Offset from FLC Base Address: <tt> 0x0024</tt> */
108-
#define MXC_R_FLC_DATA ((uint32_t)0x00000030UL) /**< Offset from FLC Base Address: <tt> 0x0030</tt> */
109-
#define MXC_R_FLC_ACTRL ((uint32_t)0x00000040UL) /**< Offset from FLC Base Address: <tt> 0x0040</tt> */
106+
#define MXC_R_FLC_ADDR ((uint32_t)0x00000000UL) /**< Offset from FLC Base Address: <tt> 0x0000</tt> */
107+
#define MXC_R_FLC_CLKDIV ((uint32_t)0x00000004UL) /**< Offset from FLC Base Address: <tt> 0x0004</tt> */
108+
#define MXC_R_FLC_CTRL ((uint32_t)0x00000008UL) /**< Offset from FLC Base Address: <tt> 0x0008</tt> */
109+
#define MXC_R_FLC_INTR ((uint32_t)0x00000024UL) /**< Offset from FLC Base Address: <tt> 0x0024</tt> */
110+
#define MXC_R_FLC_DATA ((uint32_t)0x00000030UL) /**< Offset from FLC Base Address: <tt> 0x0030</tt> */
111+
#define MXC_R_FLC_ACTRL ((uint32_t)0x00000040UL) /**< Offset from FLC Base Address: <tt> 0x0040</tt> */
110112
/**@} end of group flc_registers */
111113

112114
/**
@@ -115,8 +117,8 @@ typedef struct {
115117
* @brief Flash Write Address.
116118
* @{
117119
*/
118-
#define MXC_F_FLC_ADDR_ADDR_POS 0 /**< ADDR_ADDR Position */
119-
#define MXC_F_FLC_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */
120+
#define MXC_F_FLC_ADDR_ADDR_POS 0 /**< ADDR_ADDR Position */
121+
#define MXC_F_FLC_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */
120122

121123
/**@} end of group FLC_ADDR_Register */
122124

@@ -127,8 +129,8 @@ typedef struct {
127129
* MHz clock for Flash controller.
128130
* @{
129131
*/
130-
#define MXC_F_FLC_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */
131-
#define MXC_F_FLC_CLKDIV_CLKDIV ((uint32_t)(0xFFUL << MXC_F_FLC_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */
132+
#define MXC_F_FLC_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */
133+
#define MXC_F_FLC_CLKDIV_CLKDIV ((uint32_t)(0xFFUL << MXC_F_FLC_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */
132134

133135
/**@} end of group FLC_CLKDIV_Register */
134136

@@ -138,39 +140,39 @@ typedef struct {
138140
* @brief Flash Control Register.
139141
* @{
140142
*/
141-
#define MXC_F_FLC_CTRL_WRITE_POS 0 /**< CTRL_WRITE Position */
142-
#define MXC_F_FLC_CTRL_WRITE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_WRITE_POS)) /**< CTRL_WRITE Mask */
143+
#define MXC_F_FLC_CTRL_WRITE_POS 0 /**< CTRL_WRITE Position */
144+
#define MXC_F_FLC_CTRL_WRITE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_WRITE_POS)) /**< CTRL_WRITE Mask */
143145

144-
#define MXC_F_FLC_CTRL_MASS_ERASE_POS 1 /**< CTRL_MASS_ERASE Position */
145-
#define MXC_F_FLC_CTRL_MASS_ERASE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_MASS_ERASE_POS)) /**< CTRL_MASS_ERASE Mask */
146+
#define MXC_F_FLC_CTRL_MASS_ERASE_POS 1 /**< CTRL_MASS_ERASE Position */
147+
#define MXC_F_FLC_CTRL_MASS_ERASE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_MASS_ERASE_POS)) /**< CTRL_MASS_ERASE Mask */
146148

147-
#define MXC_F_FLC_CTRL_PAGE_ERASE_POS 2 /**< CTRL_PAGE_ERASE Position */
148-
#define MXC_F_FLC_CTRL_PAGE_ERASE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_PAGE_ERASE_POS)) /**< CTRL_PAGE_ERASE Mask */
149+
#define MXC_F_FLC_CTRL_PAGE_ERASE_POS 2 /**< CTRL_PAGE_ERASE Position */
150+
#define MXC_F_FLC_CTRL_PAGE_ERASE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_PAGE_ERASE_POS)) /**< CTRL_PAGE_ERASE Mask */
149151

150-
#define MXC_F_FLC_CTRL_WIDTH_POS 4 /**< CTRL_WIDTH Position */
151-
#define MXC_F_FLC_CTRL_WIDTH ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_WIDTH_POS)) /**< CTRL_WIDTH Mask */
152+
#define MXC_F_FLC_CTRL_WIDTH_POS 4 /**< CTRL_WIDTH Position */
153+
#define MXC_F_FLC_CTRL_WIDTH ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_WIDTH_POS)) /**< CTRL_WIDTH Mask */
152154

153-
#define MXC_F_FLC_CTRL_ERASE_CODE_POS 8 /**< CTRL_ERASE_CODE Position */
154-
#define MXC_F_FLC_CTRL_ERASE_CODE ((uint32_t)(0xFFUL << MXC_F_FLC_CTRL_ERASE_CODE_POS)) /**< CTRL_ERASE_CODE Mask */
155-
#define MXC_V_FLC_CTRL_ERASE_CODE_NOP ((uint32_t)0x0UL) /**< CTRL_ERASE_CODE_NOP Value */
156-
#define MXC_S_FLC_CTRL_ERASE_CODE_NOP (MXC_V_FLC_CTRL_ERASE_CODE_NOP << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_NOP Setting */
157-
#define MXC_V_FLC_CTRL_ERASE_CODE_ERASEPAGE ((uint32_t)0x55UL) /**< CTRL_ERASE_CODE_ERASEPAGE Value */
158-
#define MXC_S_FLC_CTRL_ERASE_CODE_ERASEPAGE (MXC_V_FLC_CTRL_ERASE_CODE_ERASEPAGE << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEPAGE Setting */
159-
#define MXC_V_FLC_CTRL_ERASE_CODE_ERASEALL ((uint32_t)0xAAUL) /**< CTRL_ERASE_CODE_ERASEALL Value */
160-
#define MXC_S_FLC_CTRL_ERASE_CODE_ERASEALL (MXC_V_FLC_CTRL_ERASE_CODE_ERASEALL << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEALL Setting */
155+
#define MXC_F_FLC_CTRL_ERASE_CODE_POS 8 /**< CTRL_ERASE_CODE Position */
156+
#define MXC_F_FLC_CTRL_ERASE_CODE ((uint32_t)(0xFFUL << MXC_F_FLC_CTRL_ERASE_CODE_POS)) /**< CTRL_ERASE_CODE Mask */
157+
#define MXC_V_FLC_CTRL_ERASE_CODE_NOP ((uint32_t)0x0UL) /**< CTRL_ERASE_CODE_NOP Value */
158+
#define MXC_S_FLC_CTRL_ERASE_CODE_NOP (MXC_V_FLC_CTRL_ERASE_CODE_NOP << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_NOP Setting */
159+
#define MXC_V_FLC_CTRL_ERASE_CODE_ERASEPAGE ((uint32_t)0x55UL) /**< CTRL_ERASE_CODE_ERASEPAGE Value */
160+
#define MXC_S_FLC_CTRL_ERASE_CODE_ERASEPAGE (MXC_V_FLC_CTRL_ERASE_CODE_ERASEPAGE << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEPAGE Setting */
161+
#define MXC_V_FLC_CTRL_ERASE_CODE_ERASEALL ((uint32_t)0xAAUL) /**< CTRL_ERASE_CODE_ERASEALL Value */
162+
#define MXC_S_FLC_CTRL_ERASE_CODE_ERASEALL (MXC_V_FLC_CTRL_ERASE_CODE_ERASEALL << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEALL Setting */
161163

162-
#define MXC_F_FLC_CTRL_BUSY_POS 24 /**< CTRL_BUSY Position */
163-
#define MXC_F_FLC_CTRL_BUSY ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_BUSY_POS)) /**< CTRL_BUSY Mask */
164+
#define MXC_F_FLC_CTRL_BUSY_POS 24 /**< CTRL_BUSY Position */
165+
#define MXC_F_FLC_CTRL_BUSY ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_BUSY_POS)) /**< CTRL_BUSY Mask */
164166

165-
#define MXC_F_FLC_CTRL_LVE_POS 25 /**< CTRL_LVE Position */
166-
#define MXC_F_FLC_CTRL_LVE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_LVE_POS)) /**< CTRL_LVE Mask */
167+
#define MXC_F_FLC_CTRL_LVE_POS 25 /**< CTRL_LVE Position */
168+
#define MXC_F_FLC_CTRL_LVE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_LVE_POS)) /**< CTRL_LVE Mask */
167169

168-
#define MXC_F_FLC_CTRL_UNLOCK_CODE_POS 28 /**< CTRL_UNLOCK_CODE Position */
169-
#define MXC_F_FLC_CTRL_UNLOCK_CODE ((uint32_t)(0xFUL << MXC_F_FLC_CTRL_UNLOCK_CODE_POS)) /**< CTRL_UNLOCK_CODE Mask */
170-
#define MXC_V_FLC_CTRL_UNLOCK_CODE_UNLOCKED ((uint32_t)0x2UL) /**< CTRL_UNLOCK_CODE_UNLOCKED Value */
171-
#define MXC_S_FLC_CTRL_UNLOCK_CODE_UNLOCKED (MXC_V_FLC_CTRL_UNLOCK_CODE_UNLOCKED << MXC_F_FLC_CTRL_UNLOCK_CODE_POS) /**< CTRL_UNLOCK_CODE_UNLOCKED Setting */
172-
#define MXC_V_FLC_CTRL_UNLOCK_CODE_LOCKED ((uint32_t)0x3UL) /**< CTRL_UNLOCK_CODE_LOCKED Value */
173-
#define MXC_S_FLC_CTRL_UNLOCK_CODE_LOCKED (MXC_V_FLC_CTRL_UNLOCK_CODE_LOCKED << MXC_F_FLC_CTRL_UNLOCK_CODE_POS) /**< CTRL_UNLOCK_CODE_LOCKED Setting */
170+
#define MXC_F_FLC_CTRL_UNLOCK_CODE_POS 28 /**< CTRL_UNLOCK_CODE Position */
171+
#define MXC_F_FLC_CTRL_UNLOCK_CODE ((uint32_t)(0xFUL << MXC_F_FLC_CTRL_UNLOCK_CODE_POS)) /**< CTRL_UNLOCK_CODE Mask */
172+
#define MXC_V_FLC_CTRL_UNLOCK_CODE_UNLOCKED ((uint32_t)0x2UL) /**< CTRL_UNLOCK_CODE_UNLOCKED Value */
173+
#define MXC_S_FLC_CTRL_UNLOCK_CODE_UNLOCKED (MXC_V_FLC_CTRL_UNLOCK_CODE_UNLOCKED << MXC_F_FLC_CTRL_UNLOCK_CODE_POS) /**< CTRL_UNLOCK_CODE_UNLOCKED Setting */
174+
#define MXC_V_FLC_CTRL_UNLOCK_CODE_LOCKED ((uint32_t)0x3UL) /**< CTRL_UNLOCK_CODE_LOCKED Value */
175+
#define MXC_S_FLC_CTRL_UNLOCK_CODE_LOCKED (MXC_V_FLC_CTRL_UNLOCK_CODE_LOCKED << MXC_F_FLC_CTRL_UNLOCK_CODE_POS) /**< CTRL_UNLOCK_CODE_LOCKED Setting */
174176

175177
/**@} end of group FLC_CTRL_Register */
176178

@@ -180,17 +182,17 @@ typedef struct {
180182
* @brief Flash Interrupt Register.
181183
* @{
182184
*/
183-
#define MXC_F_FLC_INTR_DONE_POS 0 /**< INTR_DONE Position */
184-
#define MXC_F_FLC_INTR_DONE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONE_POS)) /**< INTR_DONE Mask */
185+
#define MXC_F_FLC_INTR_DONE_POS 0 /**< INTR_DONE Position */
186+
#define MXC_F_FLC_INTR_DONE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONE_POS)) /**< INTR_DONE Mask */
185187

186-
#define MXC_F_FLC_INTR_ACCESS_FAIL_POS 1 /**< INTR_ACCESS_FAIL Position */
187-
#define MXC_F_FLC_INTR_ACCESS_FAIL ((uint32_t)(0x1UL << MXC_F_FLC_INTR_ACCESS_FAIL_POS)) /**< INTR_ACCESS_FAIL Mask */
188+
#define MXC_F_FLC_INTR_ACCESS_FAIL_POS 1 /**< INTR_ACCESS_FAIL Position */
189+
#define MXC_F_FLC_INTR_ACCESS_FAIL ((uint32_t)(0x1UL << MXC_F_FLC_INTR_ACCESS_FAIL_POS)) /**< INTR_ACCESS_FAIL Mask */
188190

189-
#define MXC_F_FLC_INTR_DONE_IE_POS 8 /**< INTR_DONE_IE Position */
190-
#define MXC_F_FLC_INTR_DONE_IE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONE_IE_POS)) /**< INTR_DONE_IE Mask */
191+
#define MXC_F_FLC_INTR_DONE_IE_POS 8 /**< INTR_DONE_IE Position */
192+
#define MXC_F_FLC_INTR_DONE_IE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONE_IE_POS)) /**< INTR_DONE_IE Mask */
191193

192-
#define MXC_F_FLC_INTR_ACCESS_FAIL_IE_POS 9 /**< INTR_ACCESS_FAIL_IE Position */
193-
#define MXC_F_FLC_INTR_ACCESS_FAIL_IE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_ACCESS_FAIL_IE_POS)) /**< INTR_ACCESS_FAIL_IE Mask */
194+
#define MXC_F_FLC_INTR_ACCESS_FAIL_IE_POS 9 /**< INTR_ACCESS_FAIL_IE Position */
195+
#define MXC_F_FLC_INTR_ACCESS_FAIL_IE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_ACCESS_FAIL_IE_POS)) /**< INTR_ACCESS_FAIL_IE Mask */
194196

195197
/**@} end of group FLC_INTR_Register */
196198

@@ -200,8 +202,8 @@ typedef struct {
200202
* @brief Flash Write Data.
201203
* @{
202204
*/
203-
#define MXC_F_FLC_DATA_DATA_POS 0 /**< DATA_DATA Position */
204-
#define MXC_F_FLC_DATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_DATA_DATA_POS)) /**< DATA_DATA Mask */
205+
#define MXC_F_FLC_DATA_DATA_POS 0 /**< DATA_DATA Position */
206+
#define MXC_F_FLC_DATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_DATA_DATA_POS)) /**< DATA_DATA Mask */
205207

206208
/**@} end of group FLC_DATA_Register */
207209

@@ -216,13 +218,13 @@ typedef struct {
216218
* this register is always zero.
217219
* @{
218220
*/
219-
#define MXC_F_FLC_ACTRL_ACTRL_POS 0 /**< ACTRL_ACTRL Position */
220-
#define MXC_F_FLC_ACTRL_ACTRL ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ACTRL_ACTRL_POS)) /**< ACTRL_ACTRL Mask */
221+
#define MXC_F_FLC_ACTRL_ACTRL_POS 0 /**< ACTRL_ACTRL Position */
222+
#define MXC_F_FLC_ACTRL_ACTRL ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ACTRL_ACTRL_POS)) /**< ACTRL_ACTRL Mask */
221223

222224
/**@} end of group FLC_ACTRL_Register */
223225

224226
#ifdef __cplusplus
225227
}
226228
#endif
227229

228-
#endif /* _FLC_REGS_H_ */
230+
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_FLC_REGS_H_

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