@@ -90,30 +90,30 @@ extern "C" {
9090#define STM_PIN_ANALOG_CONTROL (X ) (((X) >> STM_PIN_AN_CTRL_SHIFT) & STM_PIN_AN_CTRL_MASK)
9191
9292#define STM_PIN_DEFINE (FUNC_OD , PUPD , AFNUM ) ((int)(FUNC_OD) |\
93- ((STM_PIN_SPEED_MASK & STM_PIN_SPEED_MASK) << STM_PIN_SPEED_SHIFT) |\
94- (((PUPD) & STM_PIN_PUPD_MASK) << STM_PIN_PUPD_SHIFT) |\
93+ ((STM_PIN_SPEED_MASK & STM_PIN_SPEED_MASK) << STM_PIN_SPEED_SHIFT) |\
94+ (((PUPD) & STM_PIN_PUPD_MASK) << STM_PIN_PUPD_SHIFT) |\
9595 (((AFNUM) & STM_PIN_AFNUM_MASK) << STM_PIN_AFNUM_SHIFT))
9696
9797#define STM_PIN_DEFINE_SPEED (FUNC_OD , PUPD , AFNUM , SPEEDV ) ((int)(FUNC_OD) |\
98- (((SPEEDV) & STM_PIN_SPEED_MASK) << STM_PIN_SPEED_SHIFT) |\
99- (((PUPD) & STM_PIN_PUPD_MASK) << STM_PIN_PUPD_SHIFT) |\
98+ (((SPEEDV) & STM_PIN_SPEED_MASK) << STM_PIN_SPEED_SHIFT) |\
99+ (((PUPD) & STM_PIN_PUPD_MASK) << STM_PIN_PUPD_SHIFT) |\
100100 (((AFNUM) & STM_PIN_AFNUM_MASK) << STM_PIN_AFNUM_SHIFT))
101101
102102#define STM_PIN_DEFINE_EXT (FUNC_OD , PUPD , AFNUM , CHAN , INV ) \
103103 ((int)(FUNC_OD) |\
104104 ((STM_PIN_SPEED_MASK & STM_PIN_SPEED_MASK) << STM_PIN_SPEED_SHIFT) |\
105- (((PUPD) & STM_PIN_PUPD_MASK) << STM_PIN_PUPD_SHIFT) |\
106- (((AFNUM) & STM_PIN_AFNUM_MASK) << STM_PIN_AFNUM_SHIFT) |\
107- (((CHAN) & STM_PIN_CHAN_MASK) << STM_PIN_CHAN_SHIFT) |\
108- (((INV) & STM_PIN_INV_MASK) << STM_PIN_INV_SHIFT))
105+ (((PUPD) & STM_PIN_PUPD_MASK) << STM_PIN_PUPD_SHIFT) |\
106+ (((AFNUM) & STM_PIN_AFNUM_MASK) << STM_PIN_AFNUM_SHIFT) |\
107+ (((CHAN) & STM_PIN_CHAN_MASK) << STM_PIN_CHAN_SHIFT) |\
108+ (((INV) & STM_PIN_INV_MASK) << STM_PIN_INV_SHIFT))
109109
110110#define STM_PIN_DEFINE_SPEED_EXT (FUNC_OD , PUPD , AFNUM , CHAN , INV , SPEEDV ) \
111111 ((int)(FUNC_OD) |\
112- (((SPEEDV) & STM_PIN_SPEED_MASK) << STM_PIN_SPEED_SHIFT) |\
113- (((PUPD) & STM_PIN_PUPD_MASK) << STM_PIN_PUPD_SHIFT) |\
114- (((AFNUM) & STM_PIN_AFNUM_MASK) << STM_PIN_AFNUM_SHIFT) |\
115- (((CHAN) & STM_PIN_CHAN_MASK) << STM_PIN_CHAN_SHIFT) |\
116- (((INV) & STM_PIN_INV_MASK) << STM_PIN_INV_SHIFT))
112+ (((SPEEDV) & STM_PIN_SPEED_MASK) << STM_PIN_SPEED_SHIFT) |\
113+ (((PUPD) & STM_PIN_PUPD_MASK) << STM_PIN_PUPD_SHIFT) |\
114+ (((AFNUM) & STM_PIN_AFNUM_MASK) << STM_PIN_AFNUM_SHIFT) |\
115+ (((CHAN) & STM_PIN_CHAN_MASK) << STM_PIN_CHAN_SHIFT) |\
116+ (((INV) & STM_PIN_INV_MASK) << STM_PIN_INV_SHIFT))
117117
118118/*
119119 * MACROS to support the legacy definition of PIN formats
0 commit comments