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Sadik.OzerSadik.Ozer
Sadik.Ozer
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Sadik.Ozer
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Provide option to user to drive SS pin too
Signed-off-by: Sadik.Ozer <Sadik.Ozer@maximintegrated.com>
1 parent f1bce73 commit 24f4738

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5 files changed

+48
-35
lines changed

5 files changed

+48
-35
lines changed

‎targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Include/MAX32670/mxc_spi.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -173,7 +173,7 @@ struct _mxc_spi_req_t {
173173
* \ref MXC_Error_Codes for a list of return codes.
174174
*/
175175
int MXC_SPI_Init (mxc_spi_regs_t* spi, int masterMode, int quadModeUsed, int numSlaves,
176-
unsigned ssPolarity, unsigned int hz);
176+
unsigned ssPolarity, unsigned int hz, unsigned int drv_ssel);
177177

178178
/**
179179
* @brief Disable and shutdown SPI peripheral.

‎targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SPI/spi_me15.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -49,7 +49,7 @@
4949
/* **** Functions **** */
5050

5151
int MXC_SPI_Init(mxc_spi_regs_t* spi, int masterMode, int quadModeUsed, int numSlaves,
52-
unsigned ssPolarity, unsigned int hz)
52+
unsigned ssPolarity, unsigned int hz, unsigned int drv_ssel)
5353
{
5454
int spi_num;
5555

@@ -87,7 +87,7 @@ int MXC_SPI_Init(mxc_spi_regs_t* spi, int masterMode, int quadModeUsed, int numS
8787
return E_NO_DEVICE;
8888
}
8989

90-
return MXC_SPI_RevA_Init ((mxc_spi_reva_regs_t*) spi, masterMode, quadModeUsed, numSlaves, ssPolarity, hz);
90+
return MXC_SPI_RevA_Init ((mxc_spi_reva_regs_t*) spi, masterMode, quadModeUsed, numSlaves, ssPolarity, hz, drv_ssel);
9191
}
9292

9393
int MXC_SPI_Shutdown(mxc_spi_regs_t* spi)

‎targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SPI/spi_reva.c‎

Lines changed: 38 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -61,6 +61,7 @@ typedef struct {
6161
int channelRx;
6262
bool txrx_req;
6363
uint8_t req_done;
64+
unsigned drv_ssel;
6465
} spi_req_reva_state_t;
6566

6667
/* states whether to use call back or not */
@@ -76,7 +77,7 @@ static int MXC_SPI_RevA_TransSetup (mxc_spi_reva_req_t * req);
7677

7778

7879
int MXC_SPI_RevA_Init (mxc_spi_reva_regs_t* spi, int masterMode, int quadModeUsed, int numSlaves,
79-
unsigned ssPolarity, unsigned int hz)
80+
unsigned ssPolarity, unsigned int hz, unsigned drv_ssel)
8081
{
8182
int spi_num;
8283

@@ -87,6 +88,7 @@ int MXC_SPI_RevA_Init (mxc_spi_reva_regs_t* spi, int masterMode, int quadModeUse
8788
states[spi_num].last_size = 0;
8889
states[spi_num].ssDeassert = 1;
8990
states[spi_num].defaultTXData = 0;
91+
states[spi_num].drv_ssel = drv_ssel;
9092

9193
spi->ctrl0 = (MXC_F_SPI_REVA_CTRL0_EN);
9294
spi->sstime = ( (0x1 << MXC_F_SPI_REVA_SSTIME_PRE_POS) |
@@ -109,22 +111,25 @@ int MXC_SPI_RevA_Init (mxc_spi_reva_regs_t* spi, int masterMode, int quadModeUse
109111
// Clear the interrupts
110112
spi->intfl = spi->intfl;
111113

112-
if (numSlaves == 1) {
113-
spi->ctrl0 |= MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0;
114-
}
115-
116-
if (numSlaves == 2) {
117-
spi->ctrl0 |= (MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS1);
118-
}
119-
120-
if (numSlaves == 3) {
121-
spi->ctrl0 |= (MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS1 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS2);
122-
}
123-
124-
if (numSlaves == 4) {
125-
spi->ctrl0 |= (MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS1 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS2 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS3);
114+
// Driver will drive SS pin?
115+
if (states[spi_num].drv_ssel) {
116+
if (numSlaves == 1) {
117+
spi->ctrl0 |= MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0;
118+
}
119+
120+
else if (numSlaves == 2) {
121+
spi->ctrl0 |= (MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS1);
122+
}
123+
124+
else if (numSlaves == 3) {
125+
spi->ctrl0 |= (MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS1 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS2);
126+
}
127+
128+
else if (numSlaves == 4) {
129+
spi->ctrl0 |= (MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS1 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS2 | MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS3);
130+
}
126131
}
127-
132+
128133
//set quad mode
129134
if (quadModeUsed) {
130135
spi->ctrl2 |= MXC_S_SPI_REVA_CTRL2_DATA_WIDTH_QUAD;
@@ -308,11 +313,13 @@ int MXC_SPI_RevA_SetSlave (mxc_spi_reva_regs_t* spi, int ssIdx)
308313
MXC_ASSERT (spi_num >= 0);
309314
(void)spi_num;
310315

311-
// Setup the slave select
312-
// Activate chosen SS pin
313-
spi->ctrl0 |= (1 << ssIdx) << MXC_F_SPI_REVA_CTRL0_SS_ACTIVE_POS;
314-
// Deactivate all unchosen pins
315-
spi->ctrl0 &= ~MXC_F_SPI_REVA_CTRL0_SS_ACTIVE | ((1 << ssIdx) << MXC_F_SPI_REVA_CTRL0_SS_ACTIVE_POS);
316+
if (states[spi_num].drv_ssel) {
317+
// Setup the slave select
318+
// Activate chosen SS pin
319+
spi->ctrl0 |= (1 << ssIdx) << MXC_F_SPI_REVA_CTRL0_SS_ACTIVE_POS;
320+
// Deactivate all unchosen pins
321+
spi->ctrl0 &= ~MXC_F_SPI_REVA_CTRL0_SS_ACTIVE | ((1 << ssIdx) << MXC_F_SPI_REVA_CTRL0_SS_ACTIVE_POS);
322+
}
316323
return E_NO_ERROR;
317324
}
318325

@@ -761,10 +768,12 @@ uint32_t MXC_SPI_RevA_MasterTransHandler (mxc_spi_reva_regs_t *spi, mxc_spi_reva
761768
spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi);
762769

763770
// Leave slave select asserted at the end of the transaction
764-
if (!req->ssDeassert) {
765-
spi->ctrl0 |= MXC_F_SPI_REVA_CTRL0_SS_CTRL;
771+
if (states[spi_num].drv_ssel) {
772+
if (!req->ssDeassert) {
773+
spi->ctrl0 |= MXC_F_SPI_REVA_CTRL0_SS_CTRL;
774+
}
766775
}
767-
776+
768777
retval = MXC_SPI_RevA_TransHandler(spi, req);
769778

770779
if (!states[spi_num].started) {
@@ -773,10 +782,12 @@ uint32_t MXC_SPI_RevA_MasterTransHandler (mxc_spi_reva_regs_t *spi, mxc_spi_reva
773782
}
774783

775784
// Deassert slave select at the end of the transaction
776-
if (req->ssDeassert) {
777-
spi->ctrl0 &= ~MXC_F_SPI_REVA_CTRL0_SS_CTRL;
785+
if (states[spi_num].drv_ssel) {
786+
if (req->ssDeassert) {
787+
spi->ctrl0 &= ~MXC_F_SPI_REVA_CTRL0_SS_CTRL;
788+
}
778789
}
779-
790+
780791
return retval;
781792
}
782793

‎targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SPI/spi_reva.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -74,7 +74,7 @@ struct _mxc_spi_reva_req_t {
7474
};
7575

7676
int MXC_SPI_RevA_Init (mxc_spi_reva_regs_t* spi, int masterMode, int quadModeUsed, int numSlaves,
77-
unsigned ssPolarity, unsigned int hz);
77+
unsigned ssPolarity, unsigned int hz, unsigned drv_ssel);
7878
int MXC_SPI_RevA_Shutdown (mxc_spi_reva_regs_t* spi);
7979
int MXC_SPI_RevA_ReadyForSleep (mxc_spi_reva_regs_t* spi);
8080
int MXC_SPI_RevA_SetFrequency (mxc_spi_reva_regs_t* spi, unsigned int hz);

‎targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SYS/pins_me15.c‎

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -74,12 +74,14 @@ const mxc_gpio_cfg_t gpio_cfg_uart3_flow_disable = { MXC_GPIO0, (MXC_GPIO_PIN
7474

7575
const mxc_gpio_cfg_t gpio_cfg_i2s0 = { MXC_GPIO0, (MXC_GPIO_PIN_8 | MXC_GPIO_PIN_9 | MXC_GPIO_PIN_10 | MXC_GPIO_PIN_11), MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE };
7676

77-
const mxc_gpio_cfg_t gpio_cfg_spi0 = { MXC_GPIO0, (MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3 | MXC_GPIO_PIN_4 | MXC_GPIO_PIN_5), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE };
77+
const mxc_gpio_cfg_t gpio_cfg_spi0 = { MXC_GPIO0, (MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3 | MXC_GPIO_PIN_4), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE };
78+
const mxc_gpio_cfg_t gpio_cfg_spi0_ss = { MXC_GPIO0, (MXC_GPIO_PIN_5), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE };
7879
// NOTE: SPI1 definied here with SS0 only
79-
const mxc_gpio_cfg_t gpio_cfg_spi1 = { MXC_GPIO0, (MXC_GPIO_PIN_14 | MXC_GPIO_PIN_15 | MXC_GPIO_PIN_16 | MXC_GPIO_PIN_17), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE };
80+
const mxc_gpio_cfg_t gpio_cfg_spi1 = { MXC_GPIO0, (MXC_GPIO_PIN_14 | MXC_GPIO_PIN_15 | MXC_GPIO_PIN_16), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE };
81+
const mxc_gpio_cfg_t gpio_cfg_spi1_ss = { MXC_GPIO0, (MXC_GPIO_PIN_17), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE };
8082
// NOTE: SPI2 defined here with SS0 only, and NOT SS1 and SS2
81-
const mxc_gpio_cfg_t gpio_cfg_spi2 = { MXC_GPIO1, (MXC_GPIO_PIN_1 | MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3 | MXC_GPIO_PIN_4), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE };
82-
83+
const mxc_gpio_cfg_t gpio_cfg_spi2 = { MXC_GPIO1, (MXC_GPIO_PIN_1 | MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE };
84+
const mxc_gpio_cfg_t gpio_cfg_spi2_ss = { MXC_GPIO1, (MXC_GPIO_PIN_4), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE };
8385

8486
// Timers are only defined once, depending on package, each timer could be mapped to other pins
8587
const mxc_gpio_cfg_t gpio_cfg_tmr0 = { MXC_GPIO0, (MXC_GPIO_PIN_16 | MXC_GPIO_PIN_17), MXC_GPIO_FUNC_ALT3, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO};

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