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targets:MIMXRT1050: Add QSPI Flash FLASHIAP support
Update the flash driver to support both Hyper Flash and QSPI Flash. In addition, the static function cannot be linked to SRAM even defined by AT_QUICKACCESS_SECTION_CODE macro. So remove all "static" modifier for the FLASHIAP functions. Signed-off-by: Gavin Liu <gang.liu@nxp.com>
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-55
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4 files changed

+394
-55
lines changed

‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/flash_api.c‎

Lines changed: 225 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -29,8 +29,6 @@ AT_QUICKACCESS_SECTION_CODE(void flexspi_update_lut_ram(void));
2929
AT_QUICKACCESS_SECTION_CODE(status_t flexspi_nor_write_enable_ram(uint32_t baseAddr));
3030
AT_QUICKACCESS_SECTION_CODE(status_t flexspi_nor_wait_bus_busy_ram(void));
3131
AT_QUICKACCESS_SECTION_CODE(status_t flexspi_nor_flash_erase_sector_ram(uint32_t address));
32-
AT_QUICKACCESS_SECTION_CODE(static void flexspi_lower_clock_ram(void));
33-
AT_QUICKACCESS_SECTION_CODE(static void flexspi_clock_update_ram(void));
3432
AT_QUICKACCESS_SECTION_CODE(status_t flexspi_nor_flash_page_program_ram(uint32_t address,
3533
const uint32_t *src,
3634
uint32_t size));
@@ -83,6 +81,9 @@ void *flexspi_memset(void *buf, int c, size_t n)
8381
return buf;
8482
}
8583

84+
#ifdef HYPERFLASH_BOOT
85+
AT_QUICKACCESS_SECTION_CODE(void flexspi_lower_clock_ram(void));
86+
AT_QUICKACCESS_SECTION_CODE(void flexspi_clock_update_ram(void));
8687
void flexspi_update_lut_ram(void)
8788
{
8889
flexspi_config_t config;
@@ -210,7 +211,7 @@ status_t flexspi_nor_flash_erase_sector_ram(uint32_t address)
210211
return status;
211212
}
212213

213-
static void flexspi_lower_clock_ram(void)
214+
void flexspi_lower_clock_ram(void)
214215
{
215216
unsigned int reg = 0;
216217

@@ -242,7 +243,7 @@ static void flexspi_lower_clock_ram(void)
242243
}
243244
}
244245

245-
static void flexspi_clock_update_ram(void)
246+
void flexspi_clock_update_ram(void)
246247
{
247248
/* Program finished, speed the clock to 133M. */
248249
/* Wait for bus idle before change flash configuration. */
@@ -316,6 +317,224 @@ status_t flexspi_nor_flash_page_program_ram(uint32_t address, const uint32_t *sr
316317
return status;
317318
}
318319

320+
#else
321+
AT_QUICKACCESS_SECTION_CODE(status_t flexspi_nor_enable_quad_mode_ram(void));
322+
status_t flexspi_nor_enable_quad_mode_ram(void)
323+
{
324+
flexspi_transfer_t flashXfer;
325+
uint32_t writeValue = FLASH_QUAD_ENABLE;
326+
status_t status = kStatus_Success;
327+
328+
flexspi_memset(&flashXfer, 0, sizeof(flashXfer));
329+
/* Write enable */
330+
status = flexspi_nor_write_enable_ram(0);
331+
332+
if (status != kStatus_Success) {
333+
return status;
334+
}
335+
336+
/* Enable quad mode. */
337+
flashXfer.deviceAddress = 0;
338+
flashXfer.port = kFLEXSPI_PortA1;
339+
flashXfer.cmdType = kFLEXSPI_Write;
340+
flashXfer.SeqNumber = 1;
341+
flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG;
342+
flashXfer.data = &writeValue;
343+
flashXfer.dataSize = 1;
344+
345+
status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer);
346+
if (status != kStatus_Success) {
347+
return status;
348+
}
349+
350+
status = flexspi_nor_wait_bus_busy_ram();
351+
352+
/* Do software reset. */
353+
FLEXSPI_SoftwareReset(FLEXSPI);
354+
355+
return status;
356+
}
357+
358+
void flexspi_update_lut_ram(void)
359+
{
360+
flexspi_config_t config;
361+
362+
flexspi_memset(&config, 0, sizeof(config));
363+
364+
/*Get FLEXSPI default settings and configure the flexspi. */
365+
FLEXSPI_GetDefaultConfig(&config);
366+
367+
/*Set AHB buffer size for reading data through AHB bus. */
368+
config.ahbConfig.enableAHBPrefetch = true;
369+
config.ahbConfig.enableAHBBufferable = true;
370+
config.ahbConfig.enableReadAddressOpt = true;
371+
config.ahbConfig.enableAHBCachable = true;
372+
config.rxSampleClock = kFLEXSPI_ReadSampleClkLoopbackFromDqsPad;
373+
FLEXSPI_Init(FLEXSPI, &config);
374+
375+
/* Configure flash settings according to serial flash feature. */
376+
FLEXSPI_SetFlashConfig(FLEXSPI, &deviceconfig, kFLEXSPI_PortA1);
377+
378+
/* Update LUT table. */
379+
FLEXSPI_UpdateLUT(FLEXSPI, 0, customLUT, CUSTOM_LUT_LENGTH);
380+
381+
/* Do software reset. */
382+
FLEXSPI_SoftwareReset(FLEXSPI);
383+
/* Wait for bus idle. */
384+
while (!FLEXSPI_GetBusIdleStatus(FLEXSPI)) {
385+
}
386+
flexspi_nor_enable_quad_mode_ram();
387+
}
388+
389+
status_t flexspi_nor_write_enable_ram(uint32_t baseAddr)
390+
{
391+
flexspi_transfer_t flashXfer;
392+
status_t status = kStatus_Success;
393+
394+
flexspi_memset(&flashXfer, 0, sizeof(flashXfer));
395+
/* Write enable */
396+
flashXfer.deviceAddress = baseAddr;
397+
flashXfer.port = kFLEXSPI_PortA1;
398+
flashXfer.cmdType = kFLEXSPI_Command;
399+
flashXfer.SeqNumber = 1;
400+
flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITEENABLE;
401+
402+
status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer);
403+
404+
return status;
405+
}
406+
407+
status_t flexspi_nor_wait_bus_busy_ram(void)
408+
{
409+
/* Wait status ready. */
410+
bool isBusy;
411+
uint32_t readValue;
412+
status_t status = kStatus_Success;
413+
flexspi_transfer_t flashXfer;
414+
415+
flexspi_memset(&flashXfer, 0, sizeof(flashXfer));
416+
417+
flashXfer.deviceAddress = 0;
418+
flashXfer.port = kFLEXSPI_PortA1;
419+
flashXfer.cmdType = kFLEXSPI_Read;
420+
flashXfer.SeqNumber = 1;
421+
flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READSTATUSREG;
422+
flashXfer.data = &readValue;
423+
flashXfer.dataSize = 1;
424+
425+
do {
426+
status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer);
427+
428+
if (status != kStatus_Success) {
429+
return status;
430+
}
431+
if (FLASH_BUSY_STATUS_POL) {
432+
if (readValue & (1U << FLASH_BUSY_STATUS_OFFSET)) {
433+
isBusy = true;
434+
} else {
435+
isBusy = false;
436+
}
437+
} else {
438+
if (readValue & (1U << FLASH_BUSY_STATUS_OFFSET)) {
439+
isBusy = false;
440+
} else {
441+
isBusy = true;
442+
}
443+
}
444+
445+
} while (isBusy);
446+
447+
return status;
448+
}
449+
450+
451+
status_t flexspi_nor_flash_erase_sector_ram(uint32_t address)
452+
{
453+
flexspi_transfer_t flashXfer;
454+
status_t status = kStatus_Success;
455+
456+
flexspi_memset(&flashXfer, 0, sizeof(flashXfer));
457+
458+
/* Write enable */
459+
flashXfer.deviceAddress = address;
460+
flashXfer.port = kFLEXSPI_PortA1;
461+
flashXfer.cmdType = kFLEXSPI_Command;
462+
flashXfer.SeqNumber = 1;
463+
flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITEENABLE;
464+
465+
status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer);
466+
467+
if (status != kStatus_Success) {
468+
return status;
469+
}
470+
471+
flashXfer.deviceAddress = address;
472+
flashXfer.port = kFLEXSPI_PortA1;
473+
flashXfer.cmdType = kFLEXSPI_Command;
474+
flashXfer.SeqNumber = 1;
475+
flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_ERASESECTOR;
476+
status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer);
477+
478+
if (status != kStatus_Success) {
479+
return status;
480+
}
481+
482+
status = flexspi_nor_wait_bus_busy_ram();
483+
484+
/* Do software reset. */
485+
FLEXSPI_SoftwareReset(FLEXSPI);
486+
487+
return status;
488+
}
489+
490+
status_t flexspi_nor_flash_page_program_ram(uint32_t address, const uint32_t *src, uint32_t size)
491+
{
492+
flexspi_transfer_t flashXfer;
493+
status_t status = kStatus_Success;
494+
uint32_t offset = 0;
495+
496+
flexspi_memset(&flashXfer, 0, sizeof(flashXfer));
497+
498+
while (size > 0) {
499+
/* Write enable */
500+
status = flexspi_nor_write_enable_ram(address + offset);
501+
502+
if (status != kStatus_Success) {
503+
return status;
504+
}
505+
506+
/* Prepare page program command */
507+
flashXfer.deviceAddress = address + offset;
508+
flashXfer.port = kFLEXSPI_PortA1;
509+
flashXfer.cmdType = kFLEXSPI_Write;
510+
flashXfer.SeqNumber = 1;
511+
flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD;
512+
flashXfer.data = (uint32_t *)(src + offset);
513+
flashXfer.dataSize = BOARD_FLASH_PAGE_SIZE;
514+
515+
status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer);
516+
517+
if (status != kStatus_Success) {
518+
return status;
519+
}
520+
521+
status = flexspi_nor_wait_bus_busy_ram();
522+
523+
if (status != kStatus_Success) {
524+
return status;
525+
}
526+
527+
size -= BOARD_FLASH_PAGE_SIZE;
528+
offset += BOARD_FLASH_PAGE_SIZE;
529+
}
530+
531+
/* Do software reset. */
532+
FLEXSPI_SoftwareReset(FLEXSPI);
533+
534+
return status;
535+
}
536+
537+
#endif
319538
void flexspi_nor_flash_read_data_ram(uint32_t addr, uint32_t *buffer, uint32_t size)
320539
{
321540
memcpy(buffer, (void *)addr, size);
@@ -402,12 +621,12 @@ uint32_t flash_get_page_size(const flash_t *obj)
402621

403622
uint32_t flash_get_start_address(const flash_t *obj)
404623
{
405-
return BOARD_FLASH_START_ADDR;
624+
return BOARD_FLASHIAP_START_ADDR;
406625
}
407626

408627
uint32_t flash_get_size(const flash_t *obj)
409628
{
410-
return BOARD_FLASH_SIZE;
629+
return BOARD_FLASHIAP_SIZE;
411630
}
412631

413632
uint8_t flash_get_erase_value(const flash_t *obj)

‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/device.h‎

Lines changed: 15 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -19,12 +19,24 @@
1919
#define MBED_DEVICE_H
2020

2121
#define DEVICE_ID_LENGTH 24
22-
/* 4MB reserved for mbed-os */
23-
#define BOARD_FLASH_SIZE (0x3C00000U)
24-
#define BOARD_FLASH_START_ADDR (0x60400000U)
2522

23+
#ifdef HYPERFLASH_BOOT
24+
/* 64MB HyperFlash, 4MB reserved for mbed-os */
25+
#define BOARD_FLASH_SIZE (0x4000000U)
26+
#define BOARD_FLASH_START_ADDR (0x60000000U)
27+
#define BOARD_FLASHIAP_SIZE (0x3C00000U)
28+
#define BOARD_FLASHIAP_START_ADDR (0x60400000U)
2629
#define BOARD_FLASH_PAGE_SIZE (512)
2730
#define BOARD_FLASH_SECTOR_SIZE (262144)
31+
#else
32+
/* 8MB QSPI Flash, 64KB reserved for mbed_bootloader */
33+
#define BOARD_FLASH_SIZE (0x800000U)
34+
#define BOARD_FLASH_START_ADDR (0x60000000U)
35+
#define BOARD_FLASHIAP_SIZE (0x7F0000U)
36+
#define BOARD_FLASHIAP_START_ADDR (0x60010000U)
37+
#define BOARD_FLASH_PAGE_SIZE (256)
38+
#define BOARD_FLASH_SECTOR_SIZE (4096)
39+
#endif
2840

2941
#define BOARD_ENET_PHY_ADDR (2)
3042

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