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Merge pull request #11353 from kyle-cypress/pr/psoc-reserved-resources
Add reserved resources metadata to Cypress BSPs
2 parents 335f3ad + 5e2234f commit 1c32e3c

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12 files changed

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‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list‎

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[Device="CY8C624ABZI-D44"]
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[Blocks]
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# User IO
5+
# CYBSP_USER_LED1
6+
ioss[0].port[11].pin[1]
7+
# CYBSP_USER_LED2
8+
ioss[0].port[1].pin[5]
9+
# CYBSP_USER_LED3
10+
ioss[0].port[1].pin[1]
11+
# CYBSP_USER_LED4
12+
ioss[0].port[0].pin[5]
13+
# CYBSP_USER_LED5
14+
ioss[0].port[7].pin[3]
15+
# CYBSP_USER_BTN1
16+
ioss[0].port[0].pin[4]
17+
# CYBSP_USER_BTN2
18+
ioss[0].port[1].pin[4]
19+
20+
# Debug
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# CYBSP_DEBUG_UART
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scb[5]
23+
# CYBSP_DEBUG_UART_RX
24+
ioss[0].port[5].pin[0]
25+
# CYBSP_DEBUG_UART_TX
26+
ioss[0].port[5].pin[1]
27+
# CYBSP_DEBUG_UART_RTS
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ioss[0].port[5].pin[2]
29+
# CYBSP_DEBUG_UART_CTS
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ioss[0].port[5].pin[3]
31+
32+
# WIFI
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# CYBSP_WIFI_SDIO
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sdhc[0]
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# CYBSP_WIFI_SDIO_D0
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ioss[0].port[2].pin[0]
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# CYBSP_WIFI_SDIO_D1
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ioss[0].port[2].pin[1]
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# CYBSP_WIFI_SDIO_D2
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ioss[0].port[2].pin[2]
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# CYBSP_WIFI_SDIO_D3
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ioss[0].port[2].pin[3]
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# CYBSP_WIFI_SDIO_CMD
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ioss[0].port[2].pin[4]
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# CYBSP_WIFI_SDIO_CLK
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ioss[0].port[2].pin[5]
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# CYBSP_WIFI_WL_REG_ON
48+
ioss[0].port[2].pin[6]

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_4343W/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list‎

Lines changed: 42 additions & 0 deletions
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[Device="CY8C624ABZI-D44"]
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3+
[Blocks]
4+
# User IO
5+
# CYBSP_USER_LED1
6+
ioss[0].port[1].pin[5]
7+
# CYBSP_USER_LED2
8+
ioss[0].port[13].pin[7]
9+
# CYBSP_USER_LED3
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ioss[0].port[0].pin[3]
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# CYBSP_USER_LED4
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ioss[0].port[1].pin[1]
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# CYBSP_USER_LED5
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ioss[0].port[11].pin[1]
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# CYBSP_USER_BTN1
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ioss[0].port[0].pin[4]
17+
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# Debug
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# CYBSP_DEBUG_UART
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scb[5]
21+
# CYBSP_DEBUG_UART_RX
22+
ioss[0].port[5].pin[0]
23+
# CYBSP_DEBUG_UART_TX
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ioss[0].port[5].pin[1]
25+
26+
# WIFI
27+
# CYBSP_WIFI_SDIO
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sdhc[0]
29+
# CYBSP_WIFI_SDIO_D0
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ioss[0].port[2].pin[0]
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# CYBSP_WIFI_SDIO_D1
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ioss[0].port[2].pin[1]
33+
# CYBSP_WIFI_SDIO_D2
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ioss[0].port[2].pin[2]
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# CYBSP_WIFI_SDIO_D3
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ioss[0].port[2].pin[3]
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# CYBSP_WIFI_SDIO_CMD
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ioss[0].port[2].pin[4]
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# CYBSP_WIFI_SDIO_CLK
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ioss[0].port[2].pin[5]
41+
# CYBSP_WIFI_WL_REG_ON
42+
ioss[0].port[2].pin[6]

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list‎

Lines changed: 24 additions & 0 deletions
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[Device="CY8C6347BZI-BLD53"]
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[Blocks]
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# User IO
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# CYBSP_USER_LED1
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ioss[0].port[1].pin[5]
7+
# CYBSP_USER_LED2
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ioss[0].port[13].pin[7]
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# CYBSP_USER_LED3
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ioss[0].port[0].pin[3]
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# CYBSP_USER_LED4
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ioss[0].port[1].pin[1]
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# CYBSP_USER_LED5
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ioss[0].port[11].pin[1]
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# CYBSP_USER_BTN1
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ioss[0].port[0].pin[4]
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18+
# Debug
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# CYBSP_DEBUG_UART
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scb[5]
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# CYBSP_DEBUG_UART_RX
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ioss[0].port[5].pin[0]
23+
# CYBSP_DEBUG_UART_TX
24+
ioss[0].port[5].pin[1]

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list‎

Lines changed: 42 additions & 0 deletions
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[Device="CY8C6247BZI-D54"]
2+
3+
[Blocks]
4+
# User IO
5+
# CYBSP_USER_LED1
6+
ioss[0].port[1].pin[5]
7+
# CYBSP_USER_LED2
8+
ioss[0].port[13].pin[7]
9+
# CYBSP_USER_LED3
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ioss[0].port[0].pin[3]
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# CYBSP_USER_LED4
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ioss[0].port[1].pin[1]
13+
# CYBSP_USER_LED5
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ioss[0].port[11].pin[1]
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# CYBSP_USER_BTN1
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ioss[0].port[0].pin[4]
17+
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# Debug
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# CYBSP_DEBUG_UART
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scb[5]
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# CYBSP_DEBUG_UART_RX
22+
ioss[0].port[5].pin[0]
23+
# CYBSP_DEBUG_UART_TX
24+
ioss[0].port[5].pin[1]
25+
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# WIFI
27+
# CYBSP_WIFI_SDIO
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udb[0]
29+
# CYBSP_WIFI_SDIO_D0
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ioss[0].port[2].pin[0]
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# CYBSP_WIFI_SDIO_D1
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ioss[0].port[2].pin[1]
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# CYBSP_WIFI_SDIO_D2
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ioss[0].port[2].pin[2]
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# CYBSP_WIFI_SDIO_D3
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ioss[0].port[2].pin[3]
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# CYBSP_WIFI_SDIO_CMD
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ioss[0].port[2].pin[4]
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# CYBSP_WIFI_SDIO_CLK
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ioss[0].port[2].pin[5]
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# CYBSP_WIFI_WL_REG_ON
42+
ioss[0].port[2].pin[6]

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list‎

Lines changed: 42 additions & 0 deletions
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[Device="CYB0644ABZI-D44"]
2+
3+
[Blocks]
4+
# User IO
5+
# CYBSP_USER_LED1
6+
ioss[0].port[1].pin[5]
7+
# CYBSP_USER_LED2
8+
ioss[0].port[13].pin[7]
9+
# CYBSP_USER_LED3
10+
ioss[0].port[0].pin[3]
11+
# CYBSP_USER_LED4
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ioss[0].port[1].pin[1]
13+
# CYBSP_USER_LED5
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ioss[0].port[11].pin[1]
15+
# CYBSP_USER_BTN1
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ioss[0].port[0].pin[4]
17+
18+
# Debug
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# CYBSP_DEBUG_UART
20+
scb[5]
21+
# CYBSP_DEBUG_UART_RX
22+
ioss[0].port[5].pin[0]
23+
# CYBSP_DEBUG_UART_TX
24+
ioss[0].port[5].pin[1]
25+
26+
# WIFI
27+
# CYBSP_WIFI_SDIO
28+
sdhc[0]
29+
# CYBSP_WIFI_SDIO_D0
30+
ioss[0].port[2].pin[0]
31+
# CYBSP_WIFI_SDIO_D1
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ioss[0].port[2].pin[1]
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# CYBSP_WIFI_SDIO_D2
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ioss[0].port[2].pin[2]
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# CYBSP_WIFI_SDIO_D3
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ioss[0].port[2].pin[3]
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# CYBSP_WIFI_SDIO_CMD
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ioss[0].port[2].pin[4]
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# CYBSP_WIFI_SDIO_CLK
40+
ioss[0].port[2].pin[5]
41+
# CYBSP_WIFI_WL_REG_ON
42+
ioss[0].port[2].pin[6]

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list‎

Lines changed: 34 additions & 0 deletions
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[Device="CY8C6245LQI-S3D72"]
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[Blocks]
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# User IO
5+
# CYBSP_USER_LED1
6+
ioss[0].port[11].pin[1]
7+
# CYBSP_USER_BTN1
8+
ioss[0].port[0].pin[4]
9+
10+
# Debug
11+
# CYBSP_DEBUG_UART
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scb[1]
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# CYBSP_DEBUG_UART_RX
14+
ioss[0].port[10].pin[0]
15+
# CYBSP_DEBUG_UART_TX
16+
ioss[0].port[10].pin[1]
17+
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# WIFI
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# CYBSP_WIFI_SDIO
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sdhc[0]
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# CYBSP_WIFI_SDIO_D0
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ioss[0].port[2].pin[0]
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# CYBSP_WIFI_SDIO_D1
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ioss[0].port[2].pin[1]
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# CYBSP_WIFI_SDIO_D2
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ioss[0].port[2].pin[2]
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# CYBSP_WIFI_SDIO_D3
28+
ioss[0].port[2].pin[3]
29+
# CYBSP_WIFI_SDIO_CMD
30+
ioss[0].port[2].pin[4]
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# CYBSP_WIFI_SDIO_CLK
32+
ioss[0].port[2].pin[5]
33+
# CYBSP_WIFI_WL_REG_ON
34+
ioss[0].port[2].pin[6]

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list‎

Lines changed: 34 additions & 0 deletions
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[Device="CY8C624ABZI-D44"]
2+
3+
[Blocks]
4+
# User IO
5+
# CYBSP_USER_LED1
6+
ioss[0].port[13].pin[7]
7+
# CYBSP_USER_BTN1
8+
ioss[0].port[0].pin[4]
9+
10+
# Debug
11+
# CYBSP_DEBUG_UART
12+
scb[5]
13+
# CYBSP_DEBUG_UART_RX
14+
ioss[0].port[5].pin[0]
15+
# CYBSP_DEBUG_UART_TX
16+
ioss[0].port[5].pin[1]
17+
18+
# WIFI
19+
# CYBSP_WIFI_SDIO
20+
sdhc[0]
21+
# CYBSP_WIFI_SDIO_D0
22+
ioss[0].port[2].pin[0]
23+
# CYBSP_WIFI_SDIO_D1
24+
ioss[0].port[2].pin[1]
25+
# CYBSP_WIFI_SDIO_D2
26+
ioss[0].port[2].pin[2]
27+
# CYBSP_WIFI_SDIO_D3
28+
ioss[0].port[2].pin[3]
29+
# CYBSP_WIFI_SDIO_CMD
30+
ioss[0].port[2].pin[4]
31+
# CYBSP_WIFI_SDIO_CLK
32+
ioss[0].port[2].pin[5]
33+
# CYBSP_WIFI_WL_REG_ON
34+
ioss[0].port[2].pin[6]

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list‎

Lines changed: 18 additions & 0 deletions
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[Device="CYBLE-416045-02"]
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[Blocks]
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# User IO
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# CYBSP_USER_LED1
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ioss[0].port[6].pin[3]
7+
# CYBSP_USER_LED2
8+
ioss[0].port[7].pin[1]
9+
# CYBSP_USER_BTN1
10+
ioss[0].port[0].pin[4]
11+
12+
# Debug
13+
# CYBSP_DEBUG_UART
14+
scb[5]
15+
# CYBSP_DEBUG_UART_RX
16+
ioss[0].port[5].pin[0]
17+
# CYBSP_DEBUG_UART_TX
18+
ioss[0].port[5].pin[1]

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list‎

Lines changed: 18 additions & 0 deletions
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[Device="CYB06447BZI-D54"]
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3+
[Blocks]
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# User IO
5+
# CYBSP_USER_LED1
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ioss[0].port[13].pin[7]
7+
# CYBSP_USER_LED2
8+
ioss[0].port[1].pin[5]
9+
# CYBSP_USER_BTN1
10+
ioss[0].port[0].pin[4]
11+
12+
# Debug
13+
# CYBSP_DEBUG_UART
14+
scb[5]
15+
# CYBSP_DEBUG_UART_RX
16+
ioss[0].port[5].pin[0]
17+
# CYBSP_DEBUG_UART_TX
18+
ioss[0].port[5].pin[1]

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list‎

Lines changed: 38 additions & 0 deletions
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[Device="CY8C6247BZI-D54"]
2+
3+
[Blocks]
4+
# User IO
5+
# CYBSP_USER_LED1
6+
ioss[0].port[0].pin[3]
7+
# CYBSP_USER_LED2
8+
ioss[0].port[1].pin[1]
9+
# CYBSP_USER_LED3
10+
ioss[0].port[10].pin[6]
11+
# CYBSP_USER_BTN1
12+
ioss[0].port[0].pin[4]
13+
14+
# Debug
15+
# CYBSP_DEBUG_UART
16+
scb[6]
17+
# CYBSP_DEBUG_UART_RX
18+
ioss[0].port[13].pin[0]
19+
# CYBSP_DEBUG_UART_TX
20+
ioss[0].port[13].pin[1]
21+
22+
# WIFI
23+
# CYBSP_WIFI_SDIO
24+
udb[0]
25+
# CYBSP_WIFI_SDIO_D0
26+
ioss[0].port[2].pin[0]
27+
# CYBSP_WIFI_SDIO_D1
28+
ioss[0].port[2].pin[1]
29+
# CYBSP_WIFI_SDIO_D2
30+
ioss[0].port[2].pin[2]
31+
# CYBSP_WIFI_SDIO_D3
32+
ioss[0].port[2].pin[3]
33+
# CYBSP_WIFI_SDIO_CMD
34+
ioss[0].port[2].pin[4]
35+
# CYBSP_WIFI_SDIO_CLK
36+
ioss[0].port[2].pin[5]
37+
# CYBSP_WIFI_WL_REG_ON
38+
ioss[0].port[2].pin[6]

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