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TARGET_STM32F411xE/device/TOOLCHAIN_ARM_MICRO
TARGET_STM32F429xI/device/TOOLCHAIN_ARM_MICRO
TARGET_STM32F439xI/device/TOOLCHAIN_ARM_MICRO
TARGET_STM32F746xG/device/TOOLCHAIN_ARM_MICRO
TARGET_STM32F756xG/device/TOOLCHAIN_ARM_MICRO
TARGET_STM32F767xI/device/TOOLCHAIN_ARM_MICRO
TARGET_STM32H7/TARGET_STM32H743xI/device/TOOLCHAIN_ARM_MICRO
TARGET_STM32L475xG/device/TOOLCHAIN_ARM_MICRO
TARGET_STM32L476xG/device/TOOLCHAIN_ARM_MICRO
TARGET_STM32L486xG/device/TOOLCHAIN_ARM_MICRO Expand file tree Collapse file tree 10 files changed +99
-35
lines changed Original file line number Diff line number Diff line change 5454; Total: 102 vectors = 408 bytes (0x198) to be reserved in RAM
5555#define VECTOR_SIZE 0x198
5656
57- #define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE)
57+ #define MBED_CRASH_REPORT_RAM_SIZE 0x100
58+
59+ #define MBED_IRAM1_START (MBED_RAM_START + VECTOR_SIZE + MBED_CRASH_REPORT_RAM_SIZE)
60+ #define MBED_IRAM1_SIZE (MBED_RAM_SIZE - VECTOR_SIZE - MBED_CRASH_REPORT_RAM_SIZE)
61+
62+
63+ #define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE+MBED_CRASH_REPORT_RAM_SIZE)
5864
5965LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
6066
@@ -64,7 +70,10 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
6470 .ANY (+RO)
6571 }
6672
67- RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data
73+ RW_m_crash_data (MBED_RAM_START+VECTOR_SIZE) EMPTY MBED_CRASH_REPORT_RAM_SIZE { ; RW data
74+ }
75+
76+ RW_IRAM1 MBED_IRAM1_START MBED_IRAM1_SIZE { ; RW data
6877 .ANY (+RW +ZI)
6978 }
7079
Original file line number Diff line number Diff line change 3737 #define MBED_APP_SIZE 0x200000
3838#endif
3939
40- ;256 KB SRAM (0x40000 )
40+ ;256 KB SRAM (0x30000 + 0x10000 )
4141#if !defined(MBED_RAM_START)
4242 #define MBED_RAM_START 0x20000000
4343#endif
4444
4545#if !defined(MBED_RAM_SIZE)
46- #define MBED_RAM_SIZE 0x20000 ; (?)
46+ #define MBED_RAM_SIZE 0x30000
4747#endif
4848
4949
5454; Total: 107 vectors = 428 bytes (0x1AC) 8-byte aligned = 0x1B0 (0x1AC + 0x4) to be reserved in RAM
5555#define VECTOR_SIZE 0x1B0
5656
57- #define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE)
57+ #define MBED_CRASH_REPORT_RAM_SIZE 0x100
58+ #define MBED_IRAM1_START (MBED_RAM_START + VECTOR_SIZE + MBED_CRASH_REPORT_RAM_SIZE)
59+ #define MBED_IRAM1_SIZE (MBED_RAM_SIZE - VECTOR_SIZE - MBED_CRASH_REPORT_RAM_SIZE)
60+
61+ #define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE + VECTOR_SIZE + MBED_CRASH_REPORT_RAM_SIZE)
5862
5963LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
6064
@@ -64,7 +68,10 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
6468 .ANY (+RO)
6569 }
6670
67- RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data
71+ RW_m_crash_data (MBED_RAM_START+VECTOR_SIZE) EMPTY MBED_CRASH_REPORT_RAM_SIZE { ; RW data
72+ }
73+
74+ RW_IRAM1 MBED_IRAM1_START MBED_IRAM1_SIZE { ; RW data
6875 .ANY (+RW +ZI)
6976 }
7077
@@ -74,4 +81,3 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
7481 ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack
7582 }
7683}
77-
Original file line number Diff line number Diff line change 5858; should match ER_IROM1::RESET/4 and cmsis_nvic.h::NVIC_NUM_VECTORS
5959#define VECTOR_SIZE 0x1B0
6060
61- #define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE)
61+ #define MBED_CRASH_REPORT_RAM_SIZE 0x100
62+ #define MBED_IRAM1_START (MBED_RAM_START + VECTOR_SIZE + MBED_CRASH_REPORT_RAM_SIZE)
63+ #define MBED_IRAM1_SIZE (MBED_RAM_SIZE - VECTOR_SIZE - MBED_CRASH_REPORT_RAM_SIZE)
64+
65+ #define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE + VECTOR_SIZE + MBED_CRASH_REPORT_RAM_SIZE)
6266
6367LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
6468
@@ -67,16 +71,19 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
6771 *(InRoot$$Sections)
6872 .ANY (+RO)
6973 }
70-
71- RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data
74+
75+ RW_m_crash_data (MBED_RAM_START+VECTOR_SIZE) EMPTY MBED_CRASH_REPORT_RAM_SIZE { ; RW data
76+ }
77+
78+ RW_IRAM1 MBED_IRAM1_START MBED_IRAM1_SIZE { ; RW data
7279 .ANY (+RW +ZI)
7380 }
7481
75- RW_IRAM2 MBED_RAM2_START MBED_RAM2_SIZE {
82+ RW_IRAM2 MBED_RAM2_START MBED_RAM2_SIZE {
7683 .ANY (+RW +ZI)
7784 }
7885
79- ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
86+ ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
8087 }
8188
8289 ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack
Original file line number Diff line number Diff line change 4343#endif
4444
4545#if !defined(MBED_RAM_SIZE)
46- #define MBED_RAM_SIZE 0x50000
46+ #define MBED_RAM_SIZE 0x00050000
4747#endif
4848
4949
5353
5454; Total: 114 vectors = 456 bytes (0x1C8) to be reserved in RAM
5555#define VECTOR_SIZE 0x1C8
56+ #define MBED_CRASH_REPORT_RAM_SIZE 0x100
57+ #define MBED_IRAM1_START (MBED_RAM_START + VECTOR_SIZE + MBED_CRASH_REPORT_RAM_SIZE)
58+ #define MBED_IRAM1_SIZE (MBED_RAM_SIZE - VECTOR_SIZE - MBED_CRASH_REPORT_RAM_SIZE)
5659
57- #define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+ VECTOR_SIZE)
60+ #define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE + VECTOR_SIZE + MBED_CRASH_REPORT_RAM_SIZE )
5861
5962LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
6063
@@ -64,7 +67,10 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
6467 .ANY (+RO)
6568 }
6669
67- RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data
70+ RW_m_crash_data (MBED_RAM_START+VECTOR_SIZE) EMPTY MBED_CRASH_REPORT_RAM_SIZE { ; RW data
71+ }
72+
73+ RW_IRAM1 MBED_IRAM1_START MBED_IRAM1_SIZE { ; RW data
6874 .ANY (+RW +ZI)
6975 }
7076
Original file line number Diff line number Diff line change 3232 #define MBED_APP_START 0x08000000
3333#endif
3434
35- ; STM32F746xG : 1024 KB FLASH (0x100000)
35+ ; STM32F756xG : 1024 KB FLASH (0x100000)
3636#if !defined(MBED_APP_SIZE)
3737 #define MBED_APP_SIZE 0x100000
3838#endif
5353
5454; Total: 114 vectors = 456 bytes (0x1C8) to be reserved in RAM
5555#define VECTOR_SIZE 0x1C8
56+ #define MBED_CRASH_REPORT_RAM_SIZE 0x100
57+ #define MBED_IRAM1_START (MBED_RAM_START + VECTOR_SIZE + MBED_CRASH_REPORT_RAM_SIZE)
58+ #define MBED_IRAM1_SIZE (MBED_RAM_SIZE - VECTOR_SIZE - MBED_CRASH_REPORT_RAM_SIZE)
5659
57- #define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+ VECTOR_SIZE)
60+ #define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE + VECTOR_SIZE + MBED_CRASH_REPORT_RAM_SIZE )
5861
5962LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
6063
@@ -64,7 +67,10 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
6467 .ANY (+RO)
6568 }
6669
67- RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data
70+ RW_m_crash_data (MBED_RAM_START+VECTOR_SIZE) EMPTY MBED_CRASH_REPORT_RAM_SIZE { ; RW data
71+ }
72+
73+ RW_IRAM1 MBED_IRAM1_START MBED_IRAM1_SIZE { ; RW data
6874 .ANY (+RW +ZI)
6975 }
7076
Original file line number Diff line number Diff line change 5353
5454; Total: 126 vectors = 504 bytes (0x1F8) to be reserved in RAM
5555#define VECTOR_SIZE 0x1F8
56+ #define MBED_CRASH_REPORT_RAM_SIZE 0x100
57+ #define MBED_IRAM1_START (MBED_RAM_START + VECTOR_SIZE + MBED_CRASH_REPORT_RAM_SIZE)
58+ #define MBED_IRAM1_SIZE (MBED_RAM_SIZE - VECTOR_SIZE - MBED_CRASH_REPORT_RAM_SIZE)
5659
57- #define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+ VECTOR_SIZE)
60+ #define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE + VECTOR_SIZE + MBED_CRASH_REPORT_RAM_SIZE )
5861
5962LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
6063
@@ -64,7 +67,10 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
6467 .ANY (+RO)
6568 }
6669
67- RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data
70+ RW_m_crash_data (MBED_RAM_START+VECTOR_SIZE) EMPTY MBED_CRASH_REPORT_RAM_SIZE { ; RW data
71+ }
72+
73+ RW_IRAM1 MBED_IRAM1_START MBED_IRAM1_SIZE { ; RW data
6874 .ANY (+RW +ZI)
6975 }
7076
Original file line number Diff line number Diff line change 3232 #define MBED_APP_START 0x08000000
3333#endif
3434
35- ; STM32F767ZI : 2048KB FLASH (0x200000)
35+ ; STM32F743xl : 2048KB FLASH (0x200000)
3636#if !defined(MBED_APP_SIZE)
3737 #define MBED_APP_SIZE 0x200000
3838#endif
5353
5454; 166 vectors = 664 bytes (0x298) to be reserved in RAM
5555#define VECTOR_SIZE 0x298
56+ #define MBED_CRASH_REPORT_RAM_SIZE 0x100
57+ #define MBED_IRAM1_START (MBED_RAM_START + VECTOR_SIZE + MBED_CRASH_REPORT_RAM_SIZE)
58+ #define MBED_IRAM1_SIZE (MBED_RAM_SIZE - VECTOR_SIZE - MBED_CRASH_REPORT_RAM_SIZE)
5659
57- #define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+ VECTOR_SIZE)
60+ #define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE + VECTOR_SIZE + MBED_CRASH_REPORT_RAM_SIZE )
5861
5962LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
6063
@@ -64,7 +67,10 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
6467 .ANY (+RO)
6568 }
6669
67- RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data
70+ RW_m_crash_data (MBED_RAM_START+VECTOR_SIZE) EMPTY MBED_CRASH_REPORT_RAM_SIZE { ; RW data
71+ }
72+
73+ RW_IRAM1 MBED_IRAM1_START MBED_IRAM1_SIZE { ; RW data
6874 .ANY (+RW +ZI)
6975 }
7076
Original file line number Diff line number Diff line change 5858
5959; Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM
6060#define VECTOR_SIZE 0x188
61+ #define MBED_CRASH_REPORT_RAM_SIZE 0x100
62+ #define MBED_IRAM1_START (MBED_RAM_START + MBED_CRASH_REPORT_RAM_SIZE)
63+ #define MBED_IRAM1_SIZE (MBED_RAM_SIZE - MBED_CRASH_REPORT_RAM_SIZE)
6164
62- #define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE)
65+ #define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE + MBED_CRASH_REPORT_RAM_SIZE )
6366
6467LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
6568
@@ -69,11 +72,14 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
6972 .ANY (+RO)
7073 }
7174
72- RW_IRAM1 MBED_RAM_START MBED_RAM_SIZE {
75+ RW_m_crash_data MBED_RAM_START EMPTY MBED_CRASH_REPORT_RAM_SIZE { ; RW data
76+ }
77+
78+ RW_IRAM1 MBED_IRAM1_START MBED_IRAM1_SIZE { ; RW data
7379 .ANY (+RW +ZI)
7480 }
75-
76- RW_IRAM2 (MBED_RAM2_START+VECTOR_SIZE) (MBED_RAM2_START- MBED_RAM2_SIZE) {
81+
82+ RW_IRAM2 (MBED_RAM2_START+VECTOR_SIZE) (MBED_RAM2_SIZE-VECTOR_SIZE ) {
7783 .ANY (+RW +ZI)
7884 }
7985
Original file line number Diff line number Diff line change 5858
5959; Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM
6060#define VECTOR_SIZE 0x188
61+ #define MBED_CRASH_REPORT_RAM_SIZE 0x100
62+ #define MBED_IRAM1_START (MBED_RAM_START + MBED_CRASH_REPORT_RAM_SIZE)
63+ #define MBED_IRAM1_SIZE (MBED_RAM_SIZE - MBED_CRASH_REPORT_RAM_SIZE)
6164
62- #define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE)
65+ #define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE + MBED_CRASH_REPORT_RAM_SIZE )
6366
6467LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
6568
@@ -69,11 +72,14 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
6972 .ANY (+RO)
7073 }
7174
72- RW_IRAM1 MBED_RAM_START MBED_RAM_SIZE {
75+ RW_m_crash_data MBED_RAM_START EMPTY MBED_CRASH_REPORT_RAM_SIZE { ; RW data
76+ }
77+
78+ RW_IRAM1 MBED_IRAM1_START MBED_IRAM1_SIZE { ; RW data
7379 .ANY (+RW +ZI)
7480 }
75-
76- RW_IRAM2 (MBED_RAM2_START+VECTOR_SIZE) (MBED_RAM2_START- MBED_RAM2_SIZE) {
81+
82+ RW_IRAM2 (MBED_RAM2_START+VECTOR_SIZE) (MBED_RAM2_SIZE-VECTOR_SIZE ) {
7783 .ANY (+RW +ZI)
7884 }
7985
Original file line number Diff line number Diff line change 5858
5959; Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM
6060#define VECTOR_SIZE 0x188
61+ #define MBED_CRASH_REPORT_RAM_SIZE 0x100
62+ #define MBED_IRAM1_START (MBED_RAM_START + MBED_CRASH_REPORT_RAM_SIZE)
63+ #define MBED_IRAM1_SIZE (MBED_RAM_SIZE - MBED_CRASH_REPORT_RAM_SIZE)
6164
62- #define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE)
65+ #define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE + MBED_CRASH_REPORT_RAM_SIZE )
6366
6467LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
6568
@@ -69,11 +72,14 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
6972 .ANY (+RO)
7073 }
7174
72- RW_IRAM1 MBED_RAM_START MBED_RAM_SIZE {
75+ RW_m_crash_data MBED_RAM_START EMPTY MBED_CRASH_REPORT_RAM_SIZE { ; RW data
76+ }
77+
78+ RW_IRAM1 MBED_IRAM1_START MBED_IRAM1_SIZE { ; RW data
7379 .ANY (+RW +ZI)
7480 }
75-
76- RW_IRAM2 (MBED_RAM2_START+VECTOR_SIZE) (MBED_RAM2_START- MBED_RAM2_SIZE) {
81+
82+ RW_IRAM2 (MBED_RAM2_START+VECTOR_SIZE) (MBED_RAM2_SIZE-VECTOR_SIZE ) {
7783 .ANY (+RW +ZI)
7884 }
7985
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