Merge pull request #29 from ARM-software/integration

Merge osq_lock from integration to master

Author: zoybai

benchmarks/lockhammer/Makefile

@@ -31,7 +31,8 @@ TEST_TARGETS=lh_swap_mutex \
 	lh_queued_spinlock \
 	lh_empty \
 	lh_jvm_objectmonitor \
-	lh_tbb_spin_rw_mutex
+	lh_tbb_spin_rw_mutex \
+	lh_osq_lock
 
 ifeq ($(TARGET_ARCH),aarch64)
 	TEST_TARGETS+=lh_hybrid_spinlock \
@@ -55,6 +56,9 @@ lh_hybrid_spinlock: ../../ext/linux/hybrid_spinlock.h include/atomics.h ../../ex
 lh_hybrid_spinlock_fastdequeue: ../../ext/linux/hybrid_spinlock_fastdequeue.h include/atomics.h ../../ext/linux/include/lk_atomics.h src/lockhammer.c
 	${CC} ${CFLAGS} -DATOMIC_TEST=\"$<\" src/lockhammer.c -o build/$@ ${LDFLAGS}
 
+lh_osq_lock: ../../ext/linux/osq_lock.h ../../ext/linux/include/lk_atomics.h ../../ext/linux/include/lk_barrier.h ../../ext/linux/include/lk_cmpxchg.h include/atomics.h src/lockhammer.c
+	${CC} ${CFLAGS} -DATOMIC_TEST=\"$<\" src/lockhammer.c -o build/$@ ${LDFLAGS}
+
 lh_queued_spinlock: ../../ext/linux/queued_spinlock.h include/atomics.h ../../ext/linux/include/lk_atomics.h src/lockhammer.c
 	${CC} ${CFLAGS} -DATOMIC_TEST=\"$<\" src/lockhammer.c -o build/$@ ${LDFLAGS}
 

ext/linux/include/lk_atomics.h

@@ -392,3 +392,7 @@ do {									\
 
 #define arch_mcs_spin_unlock_contended(l)				\
 	smp_store_release((l), 1)
+
+#define ATOMIC_INIT(i)  { (i) }
+#define atomic_read(v)                  READ_ONCE((v)->counter)
+#define atomic_set(v, i)                WRITE_ONCE(((v)->counter), (i))

ext/linux/include/lk_barrier.h

@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+/* Based on Linux kernel 4.16.10
+ * arch/arm64/include/asm/barrier.h
+ * arch/x86/include/asm/barrier.h
+ * https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git/commit/?h=v4.16.10&id=b3fdf8284efbc5020dfbd0a28150637189076115
+ */
+
+#ifndef __ASM_BARRIER_H
+#define __ASM_BARRIER_H
+
+#include "lk_cmpxchg.h"
+
+#if defined(__x86_64__)
+
+#define mb() 	asm volatile("mfence":::"memory")
+#define rmb()	asm volatile("lfence":::"memory")
+#define wmb()	asm volatile("sfence" ::: "memory")
+#define dma_rmb()	barrier()
+#define dma_wmb()	barrier()
+#define smp_mb()	asm volatile("lock; addl $0,-4(%%rsp)" ::: "memory", "cc")
+#define smp_rmb()	dma_rmb()
+#define smp_wmb()	barrier()
+#define smp_store_mb(var, value) do { (void)xchg(&var, value); } while (0)
+
+
+/* Atomic operations are already serializing on x86 */
+#define __smp_mb__before_atomic()	barrier()
+#define __smp_mb__after_atomic()	barrier()
+
+
+#elif defined(__aarch64__)
+
+#define isb()		asm volatile("isb" : : : "memory")
+#define dmb(opt)	asm volatile("dmb " #opt : : : "memory")
+#define dsb(opt)	asm volatile("dsb " #opt : : : "memory")
+#define psb_csync()	asm volatile("hint #17" : : : "memory")
+#define csdb()		asm volatile("hint #20" : : : "memory")
+#define mb()		dsb(sy)
+#define rmb()		dsb(ld)
+#define wmb()		dsb(st)
+#define dma_rmb()	dmb(oshld)
+#define dma_wmb()	dmb(oshst)
+#define smp_mb()	dmb(ish)
+#define smp_rmb()	dmb(ishld)
+#define smp_wmb()	dmb(ishst)
+
+#else /* No Arch */
+    /* TODO: No Arch Default */
+#endif /* __x86_64__ */
+
+#endif	/* __ASM_BARRIER_H */