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| 1 | +# Copyright (c) 2018, ARM Limited. All rights reserved. |
| 2 | +# |
| 3 | +# SPDX-License-Identifier: BSD-3-Clause |
| 4 | +# |
| 5 | +# Redistribution and use in source and binary forms, with or without |
| 6 | +# modification, are permitted provided that the following conditions are met: |
| 7 | +# |
| 8 | +# Redistributions of source code must retain the above copyright notice, this |
| 9 | +# list of conditions and the following disclaimer. |
| 10 | +# |
| 11 | +# Redistributions in binary form must reproduce the above copyright notice, this |
| 12 | +# list of conditions and the following disclaimer in the documentation and/or |
| 13 | +# other materials provided with the distribution. |
| 14 | +# |
| 15 | +# Neither the name of ARM Limited nor the names of its contributors may be used |
| 16 | +# to endorse or promote products derived from this software without specific |
| 17 | +# prior written permission. |
| 18 | +# |
| 19 | +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 20 | +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 21 | +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 22 | +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| 23 | +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 24 | +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| 25 | +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| 26 | +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR |
| 27 | +# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| 28 | +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 29 | +# |
| 30 | +# The views and conclusions contained in the software and documentation are those |
| 31 | +# of the authors and should not be interpreted as representing official policies, |
| 32 | +# either expressed or implied, of this project. |
| 33 | + |
| 34 | + |
| 35 | +## Global Settings |
| 36 | +globalcfg: |
| 37 | + execdir: ../build |
| 38 | + logfile: lockhammer.csv |
| 39 | + |
| 40 | +## Sweep Test Settings |
| 41 | +# |
| 42 | +# Common assumptions for sweeptest: |
| 43 | +# CPU Frequency = 2GHz |
| 44 | +# CPU Cycle = 0.5ns |
| 45 | +# Remote DRAM (x86_64 or aarch64, NUMA) = 100ns ~ 300ns |
| 46 | +# Page Fault (4KB, x86_64) = 2000 cycles = 1000ns |
| 47 | +# Therefore we set critical section delay (-c) to 0ns, 200ns and 1000ns |
| 48 | +# We also set post critical section delay (-p) to 5x of (-c) value |
| 49 | +# By default, sweeptest will sweep sweepargu (-t) from 1 to max core count |
| 50 | +# |
| 51 | +## |
| 52 | +sweeptest: |
| 53 | + enabled: False |
| 54 | + safemode: False |
| 55 | + cmd: |
| 56 | + - lh_cas_event_mutex |
| 57 | + - lh_cas_lockref |
| 58 | + - lh_cas_rw_lock |
| 59 | + - lh_empty |
| 60 | + - lh_event_mutex |
| 61 | + - lh_incdec_refcount |
| 62 | + - lh_jvm_objectmonitor |
| 63 | + - lh_osq_lock |
| 64 | + - lh_queued_spinlock |
| 65 | + - lh_swap_mutex |
| 66 | + - lh_tbb_spin_rw_mutex |
| 67 | + - lh_ticket_spinlock |
| 68 | + cmd_aarch64: [lh_hybrid_spinlock, lh_hybrid_spinlock_fastdequeue] |
| 69 | + cmd_x86_64: |
| 70 | + repeat: 9 |
| 71 | + sweepargu: t |
| 72 | + argumax: 0 |
| 73 | + skipsince: 48 |
| 74 | + skipstep: 8 |
| 75 | + argulist: |
| 76 | + - a: 5000 |
| 77 | + c: 0ns |
| 78 | + p: 0ns |
| 79 | + - a: 5000 |
| 80 | + c: 1000ns |
| 81 | + p: 0ns |
| 82 | + - a: 5000 |
| 83 | + c: 200ns |
| 84 | + p: 1000ns |
| 85 | + - a: 5000 |
| 86 | + c: 1000ns |
| 87 | + p: 5000ns |
| 88 | + |
| 89 | +## Unittest Settings |
| 90 | +# |
| 91 | +# Common assumptions for unittest: |
| 92 | +# Only cover functional correctness, use as least time as possible |
| 93 | +# Normal runtime should be around 1 minute |
| 94 | +# t=0 means maximum core count |
| 95 | +# |
| 96 | +## |
| 97 | +unittest: |
| 98 | + enabled: True |
| 99 | + safemode: True |
| 100 | + testcase: |
| 101 | + - cmd: |
| 102 | + - lh_cas_event_mutex |
| 103 | + - lh_cas_lockref |
| 104 | + - lh_cas_rw_lock |
| 105 | + - lh_empty |
| 106 | + - lh_event_mutex |
| 107 | + - lh_incdec_refcount |
| 108 | + - lh_jvm_objectmonitor |
| 109 | + - lh_osq_lock |
| 110 | + - lh_queued_spinlock |
| 111 | + - lh_swap_mutex |
| 112 | + - lh_tbb_spin_rw_mutex |
| 113 | + - lh_ticket_spinlock |
| 114 | + cmd_aarch64: [lh_hybrid_spinlock, lh_hybrid_spinlock_fastdequeue] |
| 115 | + cmd_x86_64: |
| 116 | + t: [1, 0] |
| 117 | + a: 100 |
| 118 | + c: [0ns, 50ns] |
| 119 | + p: [0ns, 50ns] |
| 120 | + |
| 121 | + - cmd: lh_osq_lock |
| 122 | + t: [1, 0] |
| 123 | + a: 100 |
| 124 | + c: 50ns |
| 125 | + p: 0ns |
| 126 | + extra: |
| 127 | + u: 10 |
| 128 | + s: 2 |
| 129 | + |
| 130 | + - cmd: lh_tbb_spin_rw_mutex |
| 131 | + t: [1, 0] |
| 132 | + a: 100 |
| 133 | + c: 50ns |
| 134 | + p: 0ns |
| 135 | + extra: |
| 136 | + r: 4 |
| 137 | + m: 1 |
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